Abstract: The column multiplexer is for a memory matrix having memory cells arranged in rows and columns. The multiplexer includes input lines for input signals, a plurality of output lines for electrical connection to the columns of the matrix, a selective connection device for selecting, in a first operation mode, at least one output line of the plurality of output lines in such a way as to connect it selectively to the input lines. In the first operation mode, the selective connection device selects a first group of output lines among the plurality of output lines, including at least three first lines.

Abstract: A ramp generator includes a resistance ladder supplied with a constant current. Switches are closed in sequence by a shift register to provide a stepped ramp output. The constant current is controlled by referencing an on-chip bandgap voltage that is used as an input to a feedback circuit controlling current through a reference resistor ladder.

Abstract: High-Q, variable capacitance capacitor is formed by including a pocket of semiconductor material; a field insulating layer, covering the pocket; an opening in the field insulating layer, delimiting a first active area; an access region formed in the active area and extending at a distance from a first edge of the active area and adjacent to a second edge of the active area. A portion of the pocket is positioned between the access region and the first edge and forms a first plate; an insulating region extends above the portion of said body, and a polysilicon region extends above the insulating region and forms a second plate. A portion of the polysilicon region extends above the field insulating layer, parallel to the access region; a plurality of contacts are formed at a mutual distance along the portion of the polysilicon region extending above the field insulating layer.

Abstract: A class AB amplifier circuit includes a complementary output stage and a biasing circuit for biasing the output stage. The complementary output stage includes a P-type MOS transistor and an N-type MOS transistor, and the biasing circuit includes a bipolar transistor. The emitter and collector of the bipolar transistor are respectively connected to the gates of the P-type and N-type MOS transistors. The bipolar transistor is biased for controlling a bias voltage between the respective gates of the P-type and N-type MOS transistors.

Abstract: An image processing system recovers 3-D depth information for pixels of a base image representing a view of a scene. The system detects a plurality of pixels in a base image that represents a first view of a scene. The system the determines 3-D depth of the plurality of pixels in the base image by matching correspondence to a plurality of pixels in a plurality of images representing a plurality of views of the scene. The system then traces pixels in a virtual piecewise continuous depth surface by spatial propagation starting from the detected pixels in the base image by using the matching and corresponding plurality of pixels in the plurality of images to create the virtual piecewise continuous depth surface viewed from the base image, each successfully traced pixel being associated with a depth in the scene viewed from the base image.

Abstract: A process for encoding digital video signals organized in frames comprises the operations of dividing said frames into blocks starting from macroblocks subjected to motion-compensation and applying to said blocks a discrete cosine transform in such a way as to generate respective sets of coefficients. The said sets of coefficients are then assembled by being organized into sets of vectors by means of masking. Once the variance of the vectors has been detected, the vectors themselves are quantized on a number of available bits by means of a pyramid vector quantizer, associating to the vectors respective quantization pyramids having given sizes according to the variance detected and to the number of available bits. Finally, the vectors are encoded with respective codewords.

Abstract: A method for measuring with a maximum error E the phase of a substantially sinusoidal signal, of angular frequency &ohgr;=2&pgr;/T, sampled with a sampling period T/r, in which the phase is calculated as the time at which a straight line crossing two consecutive samples located on either side of a median value of the signal reaches said value, including the step of selecting number r from a range included between a value r0 and a value equal to from two to three times value r0, such that: 1 E ≥ max t ∈ [ - T r0 , 0 ] ⁢ [ t - T r0 · round ⁡ ( G · sin ⁢   ⁢ ω ⁢   ⁢ t ) round ⁡ ( sin ⁡ [ G · ω · t + 2 ⁢ π r0 ] ) - round ⁡ ( G · sin ⁢   ⁢ ω ⁢   ⁢ t ) ]

Abstract: A method and a circuit for minimizing glitches in phase-locked loops is presented. The circuit includes an input terminal connected to an input of a phase detector; a series of a charge pump generator, a filter and a voltage controlled oscillator connected downstream of the phase detector; and a frequency divider feedback connected between an output of the voltage controlled oscillator and a second input of the phase detector. The circuit provides for the inclusion of a compensation circuit connected between the charge pump generator and the filter to absorb an amount of the charge passed therethrough. This compensation circuit includes a storage element connected in series to two switches. The first switch is coupled to and controlled by an output of the charge pump and the second switch is coupled to and controlled by an output of a phase detector.

Abstract: A computer system provides on chip at least one CPU connected to another module by an address and data path, the module generating interrupt request packets with a destination address, the CPU decoding the packet, identifying a priority for the interrupt request and selectively responding to the request.

Abstract: The lateral DMOS transistor is integratable in a semiconductor power device comprising a P-type substrate and an N-type epitaxial layer. The lateral DMOS transistor comprises a source region and a drain region formed in the epitaxial layer and a body region housing the source region. Between the source region and the drain region is present an insulating region extending in depth from a top surface of the epitaxial layer as far as the substrate. The insulating region presents an interruption in a longitudinal direction defining a channeling region for a current ID flowing between the source region and the drain region of the lateral DMOS transistor.

Abstract: An inertial sensor having a stator and a rotor made of semiconductor material and electrostatically coupled together, and a microactuator also made of semiconductor material, coupled to the rotor and controlled so as to move the rotor itself and thus compensate for the position offset thereof.

Abstract: An EEPROM memory cell integrated in a semiconductor substrate comprises a floating gate MOS transistor having a source region, a drain region, and a gate region projecting from the substrate and is isolated from the substrate by an oxide layer including a thinner tunnel portion and heavily doped regions formed under said tunnel portion and extending to beneath the drain region, and a selection transistor having a source region, a drain region and a gate region, wherein said source region is heavily doped and formed simultaneously with said heavily doped regions.

Abstract: A power modulation control system using PWM pulses is provided. The system comprises an AC voltage generator, an electric load, and a control circuit incorporating at least one rectifier. The electric load is connected between the generator and the rectifier, and first and second monodirectional switches are connected in parallel with the load.

Abstract: A circuit for generating a constant pulse signal from an enabling ATD input signal may include a latch structure connected between first and second circuit nodes, with each node being coupled to a corresponding charge and discharge capacitance and being also connected to respective inputs of a logic gate. The circuit may also include a memory element coupled to the circuit nodes for filtering the enabling ATD signal and avoiding a partial discharge of one of the capacitances. An output of the logic gate is provided for generating the pulse signal independent of voltage and/or temperature variations affecting the enabling ATD signal.

Abstract: A timing and control structure for a memory, including the timing and control structure includes a first circuit that can recognize, on the basis of control signals supplied to the memory from the exterior, whether a random-access reading is to be executed, the control signals including a first control signal indicative of the presence of an address supplied to the memory from the exterior, and a second control signal that, upon switching edges of a first type, supplies to the control and timing structure a time base for the execution of the random-access readings and, upon switching edges of a second type, supplies a time base for the execution of the sequential readings, a second circuit controlled by the first circuit and upon a random-access reading, generates a first synchronism signal in response to a transition of the first type in the second control signal, a third circuit sensitive to transitions of the second type in the second control signal and which can generate a second synchronism signal upon t

Abstract: A semiconductor memory device having at least one memory cell row, each memory cell having an information storing element and a related select transistor for selecting the storing element. The select transistor includes a gate oxide region over a silicon substrate, a lower polysilicon layer and an upper polysilicon layer superimposed to the gate oxide region and electrically insulated by an intermediate dielectric layer interposed therebetween. The gate oxide regions of the select transistors of the at least one row are separated by field oxide regions, and the lower and upper polysilicon layers and the intermediate dielectric layer extend along the row over the gate oxide regions of the select transistors and over the field oxide regions. Along the row there is at least one opening in the upper polysilicon layer, intermediate dielectric layer and lower polysilicon layer, inside of which a first contact element suitable to electrically connect the lower and upper polysilicon layers is inserted.

Abstract: A thermal ink jet printhead system has a printhead with base member and a plurality of ink flow channels formed in the base member that connect to an ink reservoir and terminate in a nozzle through which ink is expelled. A heating element is associated with each ink flow channel. A monolithically integrated multiple output power driver circuit is formed as a semiconductor integrated circuit and connected to each heating element in the printhead. The multiple output driver circuit includes a power MOS transistor connected to each heating element. A reference circuit is operatively connected to each gate of the power MOS transistor and includes a reference transistor having a gate and a reference amplifier that receives as inputs a reference voltage and a source of current. An amplifier output is operatively connected to the gates of the power output transistors and the gate of the reference transistor.

Abstract: A currency note includes an identification and/or authentication element including an integrated circuit. The integrated circuit can store, securely in electronic form and accessible from outside, such information as: the value, serial number, issuer, and date of issuance.

Abstract: A circuit structure for reading data contained in an electrically programmable/erasable integrated non-volatile memory device includes a matrix of memory cells and at least one reference cell for comparison with a memory cell during a reading phase. The reference cell is incorporated in a reference cells sub-matrix which is structurally independent of the matrix of memory cells. Also provided is a conduction path between the matrix and the sub-matrix, which path includes bit lines of the sub-matrix of reference cells extended continuously into the matrix of memory cells.

Abstract: A fully digital phase aligner includes a control loop acting upon a delay line comprising at least a cascade of delay cells, each cell being individually configurable to produce one of two selectable propagation delays as a function of the logic state of a respective digital control signal. This is done by way of a shift register including a number of latches equal to the number of the cells of the delay line. An output tap of each latch of the shift register controls a respective delay cell of the delay line. A digital state machine in the control loop prevents any undesired oscillations.