Abstract: An inductive load driver circuit including a first switch that switches between a conductive state and a non-conductive state selectively applies a first power supply potential to a first side of the inductive load in response to a control signal. A second switch that switches between a non-conductive state and a conductive state selectively applies a second power supply potential to a second side of the inductive load in response to the control signal. The control signal places a control node of the second switch at a lower potential than the second side of the inductive load while the second switch is in the conductive state. In operation, a steady state current in a first direction is driven through the inductive load. The nodes of the inductive load are placed in a high impedance state, after which a steady state current is driven in a second direction through the inductive load.

Abstract: In a method for the display of teletext headers on a television receiver screen during a search for a teletext page, the teletext service uses a first group of characters comprising fixed characters and locations to receive variable characters and a second group of sets of characters, each set of characters being proper to a language and being designed to be introduced selectively at the locations of variable characters of said first group. The set of characters to be introduced into the first set is selected as soon as the first data packet enabling it to be identified is received by the TV receiver in such a way that the headers are displayed properly.

Abstract: A capacitor having an electrode with a general cup shape, including a generally horizontal bottom and vertical walls, and in electric contact by its bottom with a conductive pad, the pad extending beyond the upper surface of an insulating layer and the bottom including a complementary recess of the protruding pad portion.

Abstract: The invention provides a method for removing noise spikes from an electrical input signal having an AC component, comprising the steps of determining the actual rms value of the input signal, low pass filtering the input signal, producing a variable offset, said variable offset being a function of the actual rms value, forming a variable threshold by superimposing the variable offset to the low pass filtered signal, comparing the input signal to the variable threshold, creating a spike detection signal when the input signal passes the variable threshold, and blanking the input signal during the occurrence of the spike detection signal.

Abstract: A device for automatically converting a digital sample sequence X(n) inputted at a first frequency fe and converted into an output digital sample sequence Y(m) at a second frequency fs which is smaller than fe. An interpolator-decimator assembly having a decimation rate equal to &ggr;, selected so as to correspond to the frequency offset fe/fs is based on a polyphased filter having p tables of q elements each, said filter being designed such that samples X(n) are input at the fe frequency and table components are activated according to clocking of a second clock derived from the fe clock and wherein one clock pulse is removed.

Abstract: A method and ethernet device is disclosed and includes an extended FIFO buffer. The link partner within the ethernet system is in communication with data terminal equipment (DTE). The speed of the link partner determined using a first packet received within the FIFO buffer. Subsequent FIFO buffer reading is optimized based on the determined speed of the link partner, thus for enhancing the inter-packet gap space usage.

Abstract: The invention relates to a circuit for highly efficient driving of piezoelectric loads, comprising a linear driving circuit portion connected to the load through an inductive-resistive connection whereto a voltage waveform is applied. Advantageously, the circuit comprises further respective circuit portions, structurally independent, connected in turn to the inductive-resistive connection through respective inductors to supply a considerable fraction of the overall current required by the load in the transient and steady state respectively.

Abstract: An improved binary-weighted, switched-capacitor, charge-redistribution successive approximation analog-to-digital converter (ADC) may include an adjusting mechanism for adding a charge corresponding to one-half of the least significant bit (LSB) of the ADC to the charge stored in a switched capacitor array thereof after the sampling phase of the ADC. This is done to provide a quantization error that is evenly distributed between ±0.5 times the LSB, without the need for any additional processing clock cycles.

Abstract: A process for the manufacturing of electronic devices, including memory cells, involving forming, on a substrate of semiconductor material, multilayer stacks including a floating gate region, an intermediate dielectric region, and a control gate region; forming a protective layer extending on top of the substrate and between the multilayer stacks and having a height at least equal to the multilayer stacks. The step of forming multilayer stacks includes the step of defining the control gate region on all sides so that each control gate region is completely separate from adjacent control gate regions. The protective layer isolates the multilayer stacks from each other at the sides. Word lines of metal extend above the protective layer and are in electrical contact with the gate regions.

Abstract: A circuit for generating a pulse-width-modulated signal comprises a phase-locked loop (PLL) having a duty-cycle-insensitive phase comparator and a Sigma-Delta pulse width modulation circuit suitable for providing the voltage-controlled oscillator function of the PLL. Thereby, frequency of the signal generated is synchronized by the PLL to the specified frequency of a synchronization signal, and is thus independent of the duty cycle.

Abstract: The FAMOS memory location comprises a single floating gate (GR) overlapping an active surface of a semiconductor substrate according to at least two asymmetrical overlap profiles (PF1, PF2) so as to define at least two electrodes in the active region. Memory location programming means (MC, SW) are capable of selectively applying different predetermined sets of bias voltages to the electrodes so as to confer at least three programming logic levels on the memory location.

Abstract: A method compresses a digital image including a matrix of elements each one including a plurality of digital components of different type representing a pixel. The method includes the steps of providing an incomplete digital image wherein at least one component is missing in each element, obtaining the digital image from the incomplete digital image, splitting the digital image into a plurality of blocks and calculating, for each block, a group of DCT coefficients for the components of each type, and quantizing the DCT coefficients of each group using a corresponding quantization table scaled by a gain factor for achieving a target compression factor. The method further comprises the steps of determining an energy measure of the incomplete digital image and estimating the gain factor as a function of the energy measure, the function being determined experimentally according to the target compression factor.

Abstract: An interrupt management system includes a first down-counter which decrements in value in response to a clock signal to zero. When the value of the down-counter is equal to zero the down-counter is reset to a predetermined value X and an interrupt request signal is produced. The interrupt management system also includes a second down-counter which decrements in value from a predetermined value Y, where Y>X, in response to the clock signal. The interrupt request signal is received by a processor which services the interrupt and generates an interrupt serviced signal. The interrupt serviced signal is received by a controller which also receive the value of the second down-counter. Using the received value from the second down-counter, the controller can determine if an interrupt request has been missed and also determine the latency period for servicing an interrupt request.

Abstract: An optical cross-connect for the switching of optical channels at variable bit-rate (up to 10 Gbit/s), wavelength division multiplexed on bi-directional optical fibers forming the transmission backbone of a transport network; in particular the cross-connect can be interfaced to fibers crossing the nodes of a ring having large territorial extension, provided with protection fibers. The cross-connect includes a spatial Split & Select input stage of WDM aggregates, followed by a set of channel filters tunable on the whole optical range occupied by the channels, which jointly form a structure strictly not blocking the access to the channels by a set of bridge units whose functionality is selectable on a per-channel basis, such as for instance: transit, drop/insert, regeneration, etc. An output optical spatial Split & Select stage connects in a strictly non-blocking way the single channels from bridge units to optical multiplexers that reconstruct the WDM aggregate on the output fibers.

Abstract: An apparatus (and method) is provided that pumps (up or down) the voltage on a memory cell thereby increasing (above the logic one voltage value) or decreasing (below the logic zero voltage value) the voltage stored in the memory cell, and providing an increased differential on the bit lines during a subsequent read operation of the memory cell. When a logic one or zero voltage is coupled to the first plate of the memory cell for storage, the second plate is held at a voltage that is lower or higher, respectively (preferably a voltage that is the complement logic value of the value being stored). After the word line is deactivated (thereby decoupling the memory cell from the bit line and storing a logic one voltage value or logic zero voltage value), the voltage on the second plate is correspondently either raised or lowered. In the present invention, the second plate is raised or lowered to the precharge and equilibrate value (usually Vdd/2).

Abstract: An analog voltage pulse generator, including a first break-over component of Shockley diode type to activate a rising edge of a pulse on an output terminal and a second component of thyristor type to block the first component and deactivate the pulse.

Abstract: A storage device is provided. The storage device includes at least one memory having a parallel data bus and a parallel address bus; a first k-bit latch circuit having a parallel input and a parallel output, with the parallel input being connected to the data bus; a first k-bit shift register having a parallel input and a series output, with the parallel input being connected to the output of the first latch circuit; a second k-bit latch circuit having a parallel input and a parallel output, with the parallel output being connected to the data bus; and a second k-bit shift register having a series input and a parallel output, with the parallel output being connected to the input of the second latch circuit. In a preferred embodiment, a control circuit is coupled to the address bus, with the control circuit including address registers for storing as many address pointers as the number of k-bit shift registers.

Abstract: Process of manufacturing a semiconductor device comprising a step of forming recessed zones in a semiconductor layer of a first conductivity type, a step of oxidation for forming a gate oxide layer at the sidewalls of the recessed zones, a step of forming a polysilicon gate electrode inside the recessed zones, a step of forming body regions of a second conductivity type in the semiconductor layer between the recessed zones, and a step of forming source regions of the first conductivity type in the body regions. The step of forming recessed zones comprises a step of local oxidation of the surface of the semiconductor layer wherein the recessed zones will be formed, with an oxide growth at the semiconductor layer's cost in order to obtain thick oxide regions penetrating in the semiconductor layer, and a step of etching wherein the oxide of the thick oxide regions is removed.

Abstract: A current source with low temperature dependence includes a reference current source and a current mirror for copying the reference source current to at least one output branch. The reference current source and the current mirror may have opposite coefficients of temperature dependence and the current mirror may be a weighted mirror. The present invention is particularly applicable to the manufacture of integrated circuits.

Abstract: An operational amplifier includes a first stage, and a second stage with an input connected to an output of the first stage and an output connected to a load. The second stage includes between its input and its output a first signal path for driving the load in a first direction, and a second signal path for driving the load in the opposite direction. The first and second signal paths have substantially equal gains for small signals, substantially equal output impedances for small and large signals, and substantially equal output-current capabilities.