Abstract: In a memory integrated circuit comprising an internal circuit for the generation of a programming high voltage and comprising a first pad designed to receive a main logic supply voltage below five volts, a second specific supply pad is designed to supply the high voltage generation circuit. This enables the by application of a specific logic supply voltage with a voltage level greater than that of the main logic supply voltage in test mode or in application mode.

Abstract: A pair of complementary current sources includes a reference current source, and two complementary current mirrors having the same number of branches provided with bipolar mirror transistors. The bases of the mirror transistors of the complementary mirrors are connected to a common node. One of the complementary mirrors is connected to the reference source. An intermediate current mirror includes a first slave branch connected to the other complementary current mirror, a second slave branch connected to the reference source, and a master branch connected to the output of a trimming circuit for trimming the complementary currents for substantially equalizing the base currents of the mirror transistors of the complementary current mirrors. The input of the trimming circuit is connected to the common node.

Abstract: A circuit to control the supply of a reactive load, for supplying variable quantities of energy to the load in a predetermined manner is included in a system. The system also includes reactive components which are connected to the load by way of a controllable electronic switch and which form a resonant circuit with the load when the electronic switch is closed. Further, the system includes a circuit for activating the electronic switch, and a control unit which coordinates the operation of the controlled supply circuit and of the activation circuit in accordance with a predetermined program. The system enables the load to be driven with a particularly low power dissipated.

Abstract: The invention relates to a process for manufacturing a light sensor device in a standard CMOS process, including, implanting active areas on a semiconductor substrate to obtain a first integrated region of a corresponding photosensor; and forming a stack of layers having different thickness and refractive index layers over the photosensor to provide interferential filters for the same photosensor. At least one of the above mentioned layers is formed by a transparent metallic oxide having a high refraction index and a corresponding high dielectric constant. In this manner, due to the transparency of the high refraction index material, the design of interferential resonators is rendered more flexible making possible the use of a stack of layers including more than one high refraction index layer.

Abstract: A process for fabricating non-volatile memory cells on a semiconductor substrate includes forming a stack structure comprised of a first polysilicon layer isolated from the substrate by an oxide layer. The first polysilicon layer, oxide layer, and semiconductor substrate are cascade etched to define a first portion of a floating gate region of the cell and at least one trench bordering an active area of the memory cell. The at least one trench is filled with an isolation layer. The process further includes depositing a second polysilicon layer onto the whole exposed surface of the semiconductor, and etching the second polysilicon layer to expose the floating gate region formed in the first polysilicon layer, thereby forming extensions adjacent the above portion of the first polysilicon layer.

Abstract: An LDMOS structure is formed in a region of a first type of conductivity of a semiconductor substrate and comprises a gate, a drain region and a source region. The source region is formed by a body diffusion of a second type of conductivity within the first region, and a source diffusion of the first type of conductivity is within the body diffusion. An electrical connection diffusion of the second type of conductivity is a limited area of the source region, and extends through the source diffusion and reaches down to the body diffusion. At least one source contact is on the source diffusion and the electrical connection diffusion. The LDMOS structure further comprises a layer of silicide over the whole area of the source region short-circuiting the source diffusion and the electrical connection diffusion. The source contact is formed on the silicide layer.

Abstract: A method for simulating an integrated circuit includes dividing the integrated circuit into a plurality of independent subcircuits using a digital simulator, electrically simulating each of the independent subcircuits for a simulation result, and linking together the simulation results. By splitting the simulation of the integrated circuit into a plurality of simulations of smaller independent subcircuits, the electrical simulation is faster and can be performed in parallel since each subcircuit is independent.

Abstract: A semiconductor circuit that includes components and registration features that are electrically isolated from the components. The registration features form projecting parts that are uniformly distributed in the form of a matrix over at least part of the external surface of the circuit so as to define adjacent registration areas. In a preferred embodiment, the semiconductor circuit also includes metal registration features that are produced in at least one metallization level of the circuit. Also provided is a method of adjusting a tool so as to put it into a particular position with respect to the surface of a semiconductor circuit that has registration features defining adjacent registration areas. According to the method, an at least partial topographic record of the registration features on the surface of the semiconductor circuit is produced, and the registration features of the topographic record are brought into coincidence with reference features of a reference drawing.

Abstract: A voltage regulating device includes a comparison circuit for comparing a voltage proportional to an output voltage to a fixed reference voltage. The fixed reference voltage is received on a first input and the voltage proportional to an output voltage is received on a second input. The voltage regulating device further includes a variable resistance-forming circuit controlled by the output of the comparison circuit and disposed so that the output voltage remains substantially constant. The voltage regulating device may be supplied with a variable input voltage. The voltage regulating device further includes a second comparison circuit so that the output voltage remains substantially constant if the input voltage is greater than a threshold, and substantially equal to the input voltage if the input voltage is less than the threshold.

Abstract: Each memory cell of a memory device is connected to a bit line of a memory array and is associated with a read/rewrite amplifier connected between the bit line and a reference bit line. The bit line and the reference bit line are precharged to a predetermined precharge voltage. The content of a selected memory cell is read and refreshed based upon an associated read/rewrite amplifier. Between the precharging and the reading and refreshing, two capacitors previously charged to a charging voltage greater than the precharge voltage are respectively connected to the bit line and to the reference bit line.

Abstract: Processes are provided for fabricating a substrate having a silicon-on-insulator (SOI) or silicon-on-nothing (SON) architecture, which are applicable to the manufacture of semiconductor devices, especially transistors such as those of the MOS, CMOS, BICMOS, and HCMOS types. In the fabrication processes, a multilayer stack is grown on a substrate by non-selective full-wafer epitaxy. The multilayer stack includes a silicon layer on a Ge or SiGe layer. Active regions are defined and masked, and insulating pads are formed so as to be located around the perimeter of each of the active regions at predetermined intervals and placed against the sidewalls of the active regions. The insulating trenches are etched, and the SiGe or Ge layer is laterally etched so as to form an empty tunnel under the silicon layer. The trenches are filled with a dielectric. In the case of an SOI archiutecture, the tunnel is filled with a dielectric.

Abstract: A method for detecting displacements of a micro-electromechanical sensor including a fixed body and a mobile mass, and forming a first sensing capacitor and a second sensing capacitor having a common capacitance at rest. The first and second sensing capacitors being connected to a first input terminal and, respectively, to a first output terminal and to a second output terminal of the sensing circuit. The method includes the steps of closing a first negative-feedback loop, which is formed by the first and second sensing capacitors and by a differential amplifier, feeding an input of the differential amplifier with a staircase sensing voltage through driving capacitors so as to produce variations of an electrical driving quantity which are inversely proportional to the common sensing capacitance, and driving the sensor with the electrical driving quantity.

Abstract: A memory device includes a plurality of memory cells arranged as a matrix. Each memory cell includes a transistor and a capacitor connected in series. Each memory cell is linked to a bit line that connects the memory cells of a column. Each memory cell is also linked to a word line and to a third line. A gate of the transistor of a memory cell is linked to the word line, with each word line being linked to the gates of the transistors in a respective column. A third line is linked to the sources of the transistors of a row of memory cells. A bit line is linked to the capacitors of the transistors of a column. The voltage between the gate and the source of a transistor can thus be controlled via the word column and the third line.

Abstract: A servo circuit includes a servo channel and a processor. The servo channel recovers servo data from servo wedges that identify respective data sectors on a data-storage disk. The processor detects one of the servo wedges on spin up of the disk, i.e., while the disk is attaining or after the disk attains an operating speed. By detecting a servo wedge instead of a spin-up wedge to determine an initial head position on disk spin up, such a servo circuit allows one to increase the disk's storage capacity by reducing the number of, or altogether eliminating, spin-up servo wedges from the disk.

Abstract: Estimating the speed of movement of a mobile terminal includes estimating the impulse response of the transmission channel at a given instant, and estimating the time derivative of the estimated impulse response. Estimating the speed also includes determining of a ratio of the energy of the estimated impulse response to the energy of the estimated time derivative.

Abstract: A semiconductor integrated circuit, including a test scan arrangement has a plurality of scan chains arranged in pairs. These scan chains have input terminals for receiving test patterns, and outputs provided to compression logic such as a distributed XOR tree multiple input shift register to provide an output which is a compressed signal derived from the output test patterns. In an alternative configuration, the first scan chain of each pair is connected to the second scan chain of each pair, and the input terminal of the second scan chain becomes the output terminal. Thereby creating a longer scan chain of the first and second scan chains together with one input terminal and one output terminal. The two loads allow for efficient scanning in the first mode, or debugging to determine the position of a fault in the second mode.

Abstract: A process for cleaning an integrated circuit package surface, comprising the steps of introducing the integrated circuit inside a plasma chamber; and of exposing the integrated circuit to a physical plasma obtained starting from a gas consisting of pure argon or any other noble gas having, in the plasma state, the behavior of a halogen, for example helium. The argon pla sma is obtained using the following energization parameters: energization time, 12-13 seconds; energization power, 140-160 W; plasma chamber pressure, 190-210 millitorr; and energization frequency, between 1 kHz and 100 GHz.

Abstract: The component, fully integrated onto a monolithic substrate, includes a tuner, a demodulator, and a channel decoder. The overall filtering is carried out in two parts, a baseband analog filtering and a digital Nyquist filtering removing the information of adjacent channels. It outputs a stream of MPEG data.

Abstract: A sensing circuit for sensing a memory cell, the sensing circuit having a first circuit branch electrically connectable to the memory cell to receive a memory cell current, the first circuit branch having at least one first transistor that, when the first circuit branch is connected to the memory cell, is coupled thereto substantially in a cascode configuration. A bias current generator is operatively associated with the first transistor for forcing a bias current to flow therethrough.

Abstract: A circuit that compensates for delays induced by clock generation logic and distributed clock drivers in phase lock loop applications is disclosed. The circuit is a phase lock loop (PLL) which contains a clock synchronization circuit that operates to synchronize a transition edge of a signal generated by a frequency divider against a distributed clock signal generated by a clock output driver of the circuit. The synchronization occurs unless the clock synchronization circuit is disabled.