Abstract: A method is provided for depositing a silicon nitride layer to protect and isolate underlying layers during wet etching. The silicon nitride layer maintains the integrity of interconnect leads, bond pads, and die boundaries by acting as a wet etch stop. The silicon nitride layer stops the chemicals used in a wet etch from reaching underlying layers in the integrated circuit.

Abstract: The decimator filter includes at least three identical undersampled filters out-of-phase with each other and connected in parallel, and an interpolator connected to the output of each filter. The decimator filter includes a triple integrator having an output connected to each of the filters. Each filter defines a channel that includes in sequence an undersampling circuit, a differentiator and a multiplier. The outputs of the multipliers are connected to an adder. The input signals to each of these channels are offset by a delay equal to one period of the oversampled frequency. Each undersampling circuit and each multiplier has a second input receiving a signal from a state machine. The decimator filter improves the required phase extraction time and the precision defined in the ISDN U interface specifications. By combining the decimation filter and the extraction functions, a device is produced in a small area, which consequently, consumes low power.

Abstract: A semiconductor memory such as a flash memory, which comprises at least one two-dimensional array of memory cells with a plurality of rows and columns of memory cells grouped in a plurality of packets. The memory cells belonging to the columns of each packet are formed in a respective semiconductor region with a first type of conductivity, this region being distinct from the semiconductor regions with the first type of conductivity in which the memory cells belonging to the columns of the remaining packets are formed. The semiconductor regions with the first type of conductivity divide the set of memory cells belonging to each row into a plurality of subsets of memory cells that constitute elemental memory units which can be modified individually. Thus memory units of very small dimensions can be erased individually, without excessive overhead in terms of area.

Abstract: A head (130) for a disk storage device having a plurality of tracks (117) divided into memory cells (234), including a magnetic circuit (205, 230a, 230b, 250a, 250b) for reading the memory cells (234) in succession, the magnetic circuit (205, 230a, 230b, 250a, 250b) for reading the memory cells (234) including at least two partial reading components (206a, 230a, 250a; 206b, 230b, 250b) each for reading a portion (234a; 234b) of each memory cell (234), the portions (234a; 234b) being arranged transversely relative to the longitudinal axis (233) of the corresponding track (117).

Abstract: The forming of a contact with a deep region of a first conductivity type formed in a silicon substrate. The contact includes a doped silicon well region of the first conductivity type and an intermediary region connected between the deep layer and the well. This intermediary connection region is located under a trench. The manufacturing method enables forming of vertical devices, in particular fast bipolar transistors.

Abstract: A method for determining r error detection bits that can be associated with a word of m bits to be coded, including the step of calculating the product of a vector with m components representative of the word of m bits to be coded and of a parity control matrix of dimension r×m. The parity control matrix is such that each column of matrix includes an odd number of “1s” greater than or equal to three. The present invention also relates to a method for determining a syndrome.

Abstract: There is disclosed systems for multiplexing packetized elementary streams in a digital video recorder (DVR), methods of operating the same, and multiplexed program streams. One such system is associated with a DVR and operates to multiplex packetized elementary streams into a multiplexed program stream, the packetized elementary streams comprising PES packets of disparate size. The system is operable to (i) receive the PES packets into a memory buffer, (ii) reformat each of the received PES packets into at least one fixed-size program packet having a header and a payload, the header defining a payload content, and (iii) associate ones of the at least one fixed-size program packets into the multiplexed program stream.

Abstract: A MOSFET transistor comprising a gate made of silicon-germanium alloy, formed on a single crystal silicon substrate by means of a thin insulating layer, and drain and source regions implanted in the substrate on each side of the gate, characterized in that the gate comprises side regions presenting an increasing germanium percentage towards the sides of the gate facing the drain and source regions. Advantage: compensation of the short channel effect by locally decreasing the work function of the gate material near the drain and source regions.

Abstract: A method for extracting binary data conveyed by an incident signal is provided in which the binary data is coded in the form of a pulsatile signal whose pulses have variable lengths which are multiples of a base pulse length 1T. The incident signal may include a succession of transitions whose spacings are representative of the lengths of the pulses. The method may include an initialization phase in which the value of a base distance corresponding to the base pulse length is determined from the contents of the incident signal, and an extraction phase in which a set of reference values corresponding respectively to various multiples of the determined base distance is formulated. For a calculated current distance, the values of the data corresponding to this current distance may be determined from a comparison between the reference values and a current corrected distance.

Abstract: A method corrects the errors in a multilevel memory, by increasing the number of levels of the memory cells, instead of adding further memory cells. In other words, the present correction method is based on the principle of storing, in each multilevel memory cell, instead of a whole number b of bits in the binary word to be stored, data units which are correlated to this binary word, and are expressed in a numerical base other than binary, and not a power of two. This is carried out by converting the binary word with m bits to be stored, from the binary base, to a base n, which is not a power of two, and by associating with the converted word a correction word, which is also formed from digits with a base n; the digits of the converted and correction words are then each stored in a respective multilevel memory cell, with a number of levels which is equivalent to the numerical base used for the conversion.

Abstract: Process for producing electrical-connections on a semiconductor package containing an integrated-circuit chip and with an external protective layer having apertures that least partly expose metal electrical-connection regions, and semiconductor package provided with such metal electrical-connections. The apertures having walls are filled with a metal electrical-connection layer covering at least their walls. A metal solder drop is soldered to the connection layer so that it is not in contact with the external protective layer.

Abstract: An method of arranging address decoders in an improved manner in an integrated circuit memory is discussed. In the integrated circuit memory the address lines extending from the address circuitry of the integrated circuit memory are connected to address decoders, each word line of the memory being connected to an address decoder. The address decoders are connected to the address lines in a certain combination such that only one of the address lines is connected to adjacent address decoders. When connected in this manner the average propagation delay of each address line is substantially uniform. By reducing the maximum propagation delay in comparison with previously known arrangements of address decoders the speed at which the memory can be operated is increased.

Abstract: An area-efficient reconstruction filter removes undesirable sample images produced by current-driven digital-to-analog converters. The reconstruction filter includes: an input node for receiving the input current signal; an operational amplifier having first and second inputs and an output at which the output voltage signal is produced; a first resistor coupled between the output of the operational amplifier and the input node; a second resistor coupled to the first input of the operational amplifier; and a third resistor coupled between the input node and the second resistor. The reconstruction filter may also include a fourth resistor coupled between the input node and a reference voltage.

Abstract: A method of making an integrated circuit that is resistant to an unauthorized duplication through reverse engineering includes forming a plurality of false contacts and/or false interconnection vias in the integrated circuit. These false contacts and/or false interconnection vias are connected as true contacts and true interconnection vias by lines patterned in a metallization layer deposited over an insulating dielectric layer or multilayer through which the true contacts and/or the true interconnection vias are formed. False contacts and false vias extend in the respective dielectric layers or multilayers to a depth insufficient to reach the active areas of a semiconductor substrate for false contacts, or to a depth insufficient to reach a layer of conductive material below the dielectric layers or multilayers for false interconnection vias.

Abstract: A process produces at a predetermined metallization level at least one metal track (7) within an intertrack dielectric material (1). The process includes the steps of etching the intertrack dielectric material (1) so as to form a cavity (4) at the position of the track, depositing a conducting barrier layer (5) in the cavity (4), filling the cavity (4) with copper, and depositing a silicon nitride layer (8) on the predetermined metallization level. Between the barrier layer deposition step and the copper filling step, titanium is deposited on at least part of the barrier layer. This titanium will be transformed into TiSi2 (60) during the diffusion of the silicon from the silicon nitride layer (8).

Abstract: A system and method for communicating with an integrated circuit is provided that allows an integrated circuit to communicate debugging information and system bus transaction information with an external system. The system may include an interface protocol that provides flow control between the integrated circuit and the external system. The system may include a high-speed link and/or a JTAG link for communicating information. A link may be automatically selected by a debug circuit, or selected by an on-chip device or external system. The high-speed link enables real-time collection of trace information. Links may be memory-mapped, such that on-chip devices and other devices attached to the system bus may access the external system. The high-speed link may also operate at a rate which is integrally coupled with a rate of the processor or system bus. Further, the high-speed link may be adapted to change speeds in response to a change in operating speed of the system bus or processor.

Abstract: A bi-dimensional position sensor that can be advantageously used in the turn system controlled from the steering wheel of a vehicle. The sensor includes a permanent magnet fixed to a control lever so as to move in a plane along first and second directions and to rotate about a third direction orthogonal to the preceding ones. The permanent magnet is movable with respect to an integrated device including a first group of sensor elements arranged spaced along the first direction, a second group of sensor elements arranged spaced along the second direction and a third group of sensor elements detecting the angular position of the permanent magnet. Electronics integrated with the sensor elements generate a code associated with each position which the permanent magnet may assume and generate a control signal corresponding to the desired function.

Abstract: A device for generating synchronous numeric signals, including a first signal generator which supplies a numeric reference signal having a first frequency and a first period; and a second signal generator which generates an internal numeric signal having a second frequency and a second period, and a synchronized numeric signal. In addition, the second signal generator includes a predictor which generates, with a third period and a third frequency higher than the first frequency and the second frequency, estimated samples correlated to a current sample and to a predetermined number of former samples of the internal numeric signal. The predictor, in turn, includes a selection circuit controlled by the first signal generator for selecting one among the estimated samples in each reference period, the synchronized numeric signal being formed by the selected estimated samples.

Abstract: A non-volatile memory includes a floating gate extending in a substrate between source and drain regions. A channel region may be confined by two insulating layers. The invention is particularly applicable to EPROM, EEPROM, Flash and single-electron memories using CMOS technology.

Abstract: A semiconductor device includes multiple layers of integrated electronic components, and at least one electrical connection strip defining a fusible strip in one of the layers. An end of the fusible strip is connected to an integrated electronic component. An intermediate electrical connection and heat dissipation structure and a screen are disposed between the fusible strip and the integrated electronic component.