Abstract: A circuit device structured to enable a hierarchic form of row decoding in semiconductor memory devices of the non-volatile type and including a matrix of memory cells with sectors organized into columns, wherein each sector has a group of local word lines individually connected to a main word line running through all of the matrix sectors which have rows in common is presented. The device includes a PMOS first transistor having conduction terminals connected respectively to the main word line and the local word line, an NMOS second transistor having conduction terminals connected respectively to the local word line and the main word line, and a PMOS third transistor having conduction terminals connected respectively to the main word line and the local word line. Such a third transistor is a charge transistor that reduces the charging time for the local word line.

Abstract: A device for reading from a capacitive memory cell, including a comparator of the voltage stored in the memory cell with respect to a reference value, which exhibits a high input impedance; a refreshment means distinct from the comparator, the refreshment means having a low output impedance and being controlled by the comparator to impose a refreshment voltage to the memory cell; and means for controllably connecting the refreshment means to the memory cell.

Abstract: A fingerprint detector having a smooth sensor surface for contact with a fingerprint includes capacitive sensor plates defining an array of sensor cells below the sensor surface and tungsten ESD protection grid lines surrounding each sensor cell. The sensor surface is defined by silicon carbide and includes silicon oxide filling cavities in the silicon carbide. The cavities inherently result from processing steps, including removal of the tungsten atop the silicon carbide that is used to define the grid lines. Filling the cavities with oxide and smoothing the surface using chemical mechanical polishing provides a scratch-resistant surface and improves the sensitivity of the capacitive sensor cells.

Abstract: An integrated circuit memory fabrication process and structure, in which salicidation is performed on the periphery (and optionally on the ground lines) of a memory chip, but not on the transistors of the memory cells.

Abstract: An inkjet print head includes an ink drop emission mini-gun and a drop emission sensor integrated in a chip of semiconductor material. The mini-gun is formed by an ink chamber and a nozzle in communication with the ink chamber and the drop emission sensor includes a resistive element arranged in a position adjacent to the ink chamber. The resistance of the resistive element depends on the pressure exerted thereon, so that when the mini-gun emits an ink drop, it is subjected to a recoil movement which causes a change of pressure and hence of resistance in the resistive element; this change in resistance may be detected through suitable circuitry to identify whether and when a drop of ink has been emitted.

Abstract: An integrated circuit includes an adjustment resistor, and at least one control transistor connected to a first voltage reference. An adjustment element is connected in parallel with the adjustment resistor for adjusting a combined electrical resistance of the adjustment element and the resistor. The adjustment element is connected to the control transistor, and includes a substrate, and a MOS transistor having a source, a drain, and a gate on the substrate. The MOS transistor defines a parasitic bipolar transistor with the substrate. The adjustment element further includes a first resistor connected between the substrate and the source, and a second resistor is connected between the substrate and the drain. A diode is connected in series with the second resistor between the substrate and the drain. The gate and the source of the MOS transistor are connected together with the MOS transistor being broken down so that the adjustable element forms an electrical resistance.

Abstract: An electric low-pass filter with blocking behavior for a predetermined rejection frequency, comprising a series connection including a FIR filter and an IIR filter, with the parameters of the FIR filter being matched in essence with respect to the blocking behavior at the rejection frequency and the parameters of the IIR filter being matched in essence with respect to the low-pass behavior. It is possible with such a filter to obtain good low-pass behavior with very high attenuation of the frequency to be rejected, with relatively low circuit expenditure and high stability with respect to oscillation tendency.

Abstract: A CMOS output buffer uses feedback from a ground node to reduce ground bounce by utilizing a tolerable ground bounce limit, making it less sensitive to operating conditions and processing parameters. An input to the NMOS device of the output buffer is provided by the output of a control element which receives a first input from a pre-driver and a second input (i.e., the feedback) from the ground node.

Abstract: A digital frequency divider has a single circulating shifter register loaded with a bit sequence of variable length and having two outputs adjacent such that are output is equal to the other delayed by one clock period. The outputs are passed to a multiplexer via further logic, the multiplexer selecting one of two inputs depending on whether a clock is high or low. Program logic is provided so that the circuit is configurable for odd, even or half integer division by detecting changes in the bit sequence between 0 and 1 and selectively “deleting” the first half clock cycle when a change is detected. This allows even, odd or half integer clock division with an “even” mark space ratio.

Abstract: Herein described is a device for driving electric motors comprising a power stage with a variable duty-cycle coupled to a supply voltage. The power stage is suitable for driving the electric motor. The driving device comprises a circuit that is capable of raising the value of the input voltage of the power stage above the induced counter electromotive voltage of the motor in certain periods of time and a control device capable of activating said circuit in reply to values of the induced counter electromotive voltage greater than or comparable with the supply voltage.

Abstract: A device and a method for refreshing the voltage of a circuit line that provides the capability of bringing the circuit line to a ground voltage or to a first voltage. The method provides storing the circuit line voltage in a capacitor; and controlling, by means of the stored voltage, a switch connecting the circuit line to a second voltage of absolute value greater than the first voltage, whereby the circuit line is set to the second voltage if, during the step of storing, the circuit line was at the first voltage.

Abstract: A test handler apparatus, having a treatment area; a testing station in the treatment area; and an output unit connected to an output of the treatment area. An input unit picks singulated or stripped packages and unloads them on carrier boats in a loading zone; a conveyor mechanism transfers the carrier boats from the loading zone through the treatment area to the testing station and from the testing station to the output unit. In practice, the carrier boat forms a universal carrier which is able to contain multiple singulated or strip packages for the purpose of testing. Placing packages onto carriers with standardized dimension allows handler equipment to accommodate the packages in singulated or strip condition.

Abstract: A word recognition device uses an associative memory to store a plurality of coded words in such a way that a weight is associated with each character of the alphabet of the stored words, wherein equal weights correspond to equal characters. To perform the recognition, a dictionary of words is first chosen; this is stored in the associative memory according to a pre-determined code; a string of characters which correspond to a word to be recognized is received; a sequence of weights corresponding to the string of characters received is supplied to the associative memory; the distance between the word to be recognized and at least some of the stored words is calculated in parallel as the sum of the difference between the weights of each character of the word to be recognized and the weights of each character of the stored words; the minimum distance is identified; and the word stored in the associative memory having the minimum distance is stored.

Abstract: A method is disclosed for controlling the write head of a magnetic disk storage device. The method includes sinking current from the first terminal of the write head and sourcing current to the second terminal of the write head substantially simultaneously with sinking current from the first terminal so that a first steady state voltage level appears on the first terminal of the write head and a second steady state voltage level appears on the second terminal thereof that are approximately at a midpoint between a high reference voltage level and a low reference voltage level. The common mode voltage of the write head is substantially constant over time.

Abstract: A method and circuit are disclosed for controlling the write head of a magnetic disk storage device. The circuit includes a pull-up device coupled to a terminal of the write head, a current sink circuit which is coupled to the write head terminal and a bootstrap circuit coupled to the current sink circuit. When reversing the direction of current flow through the write head so that current is drawn from the write head from the write head terminal, the bootstrap circuit and the current sink circuit are activated. When the current in the write head nears and/or slightly surpasses the desired destination current level, the bootstrap circuit is deactivated and the pull-up device is thereafter immediately activated for a predetermined period of time.

Abstract: A circuit structure for semiconductor devices which are integrated on a semiconductor layer is provided. The structure comprises at least one MOS device and at least one capacitor element that has a bottom and a top electrode. The MOS device has conduction terminals formed in the semiconductor layer, as well as a control terminal covered with an overlying insulating layer of unreflowed oxide. The capacitor element is formed on the unreflowed oxide layer.

Abstract: An enhanced fingerprint sensing circuit in which a voltage change is applied to the body during sensing. When the person's fingerprint is being sensed, the person's body is in contact with an electrical terminal. When the sensing occurs, the voltage on the electrical terminal changes, which changes the voltage on the person's body. The pattern of the fingerprint performs two functions in the sensing circuit. In addition to being a plate of a capacitor whose distance is being sensed, it is now a source of input charge as well. The electrical effect on the cell of a voltage change on a person's finger is different at a ridge than at a valley in the fingerprint sensing circuit. Thus, the input capacitance to the sensing circuit is variable, depending upon whether a ridge or a valley is present. The sensing circuit also detects a change in its own capacitance based on the presence of a ridge or a valley.

Abstract: A portable system carried by a user for assessing movement of the user includes at least one motion sensor adjacent a portion of the user's body under observation. An analog-to-digital converter is connected to the motion sensor for converting an analog signal therefrom into a digital signal. A logic circuit is connected to the analog-to-digital converter for calculating parameters based upon the digital signal. A first fuzzy logic processing circuit is connected to the logic circuit for processing the calculated parameters and for generating corresponding fuzzy classification labels based upon movement of the portion of the user's body under observation during an interval of time. A memory is connected to the first fuzzy logic processing circuit for storing at least one of the calculated parameters and the fuzzy classification labels.

Abstract: A memory cell is formed with a buffer circuit. The output of the buffer circuit is linked to the input to form a logic latch. A write-access transistor is disposed between a first node linked to a bit line and the input of the buffer circuit. A control gate of the write-access transistor is linked to a second node linked to a write word line, and a read-access transistor is disposed between a first node linked to a bit line and a second node linked to a read word line. A control gate of the read-access transistor is linked to the output of the buffer circuit.

Abstract: A method for error control in multilevel memory cells storing a configurable number of bits. The error control is performed using an error-control code which operates, in the encoding phase, on b-bit binary strings made up of k symbols of r-bit data. When the memory cells store a number r of bits, a data symbol is formed only with the data bits stored in a memory cell. When the memory cells store a number s of bits smaller than r, a data symbol is formed with the data bits stored in a memory cell and with r-s bits having a pre-determined logic value, in which the data bits stored in the memory cell are arranged in the least significant part of the data symbol, and the r-s bits having a pre-determined logic value are arranged in the most significant part of the data symbol.