Abstract: A method for forming isolating structures in a silicon carbide layer includes depositing a masking layer on first and second portions of the silicon carbide layer, and forming openings through the masking layer to expose the first portions of the silicon carbide layer. Ions are implanted into the first portions of the silicon carbide layer. The silicon carbide layer is heated to form an oxide layer thereon having first portions on the first portions of the silicon carbide layer, and having second portions on the second portions of the silicon carbide layer. The first portions of the oxide layer are etched to form isolating regions in the silicon carbide layer.

Abstract: A servo circuit includes a servo channel and a processor. The servo channel recovers servo data from servo wedges that identify respective data sectors on a data-storage disk. On spin up of the disk, the processor detects a spin-up wedge associated with one of the servo wedges and then detects the servo wedge. Once the servo wedge is detected, a head-position circuit can read the location data from the servo wedge to determine an initial position of the read-write head. By detecting a both a spin-up wedge and a servo wedge to determine an initial head position on disk spin up, such a servo circuit often allows one to increase the disk's storage capacity by reducing the lengths of the spin-up wedges.

Abstract: A system for simplifying the programmable memory-to-logic interface in field programmable gate arrays (FPGAs) is provided. An interface may be used to isolate the general purpose routing architecture for intra-programmable logic blocks (PLBs) from the random access memory (RAM) address lines, data lines, and control lines. The PLBs and the input-output resources of the FPGA access the embedded memory (or RAM) using dedicated direct interconnects. Certain of these direct interconnects may originate from PLBs in the vicinity of the RAM. The remainder run between the input-output (IO) pads/routing and the RAM blocks. A bus routing architecture is also provided to combine the memories to emulate larger RAM blocks. This bus routing provides interconnection among RAM blocks and is isolated from the PLB routing resources.

Abstract: A field programmable logic device includes at least two independently configurable embedded memory structures. The memory structures may differ in at least one parameter, such as memory size, available configuration depths, and available configuration widths. As such, a more efficient memory utilization is provided.

Abstract: A current source using a bandgap voltage circuit includes a current gain circuit between the output of the bandgap circuit and the current output transistor. On-off control is provided by a switchable bias circuit providing an ON potential to start the bandgap and a clamping circuit opening the feedback loop.

Abstract: In an actuator device for hard disks a suspension element carries a slider that is subject to undesired vibrations which give rise to rotations of the slider with respect to a nominal position. An electrostatically controlled position-control structure is arranged between the suspension and the slider and is controlled in an active way so as to generate torsions of the platform that counter the undesired rotations. The position-control structure comprises a platform of conductive material and control electrodes arranged underneath the platform. The platform is connected to a load-bearing structure by spring elements that enable movements of roll and pitch. Four control electrodes are arranged according to the quadrants of a square and can be selectively biased for generating electrical forces acting on the platform.

Abstract: A differential amplifier circuit comprises: an amplifying section including first and second current branches and an output stage which comprises a current sinking element and a control element. The circuit also includes a current limiting section which comprises a current detecting element connected to detect the current through the current sinking element and arranged to drive the current limiting element when the detected current exceeds a predetermined threshold to inject current at the collector of the transistor in the first current branch.

Abstract: Within a capacitive fingerprint detection device, finger detection is provided by a capacitive grid overlying the fingerprint sensor electrodes to measure the absolute capacitance of the finger placed on the sensor surface. The capacitive measurement is converted to a representative frequency, which is then compared to a reference frequency or frequency range to determine whether the measured capacitance matches the expected bio-characteristics of living skin tissue. The finger detection thus provides anti-spoofing protection for the fingerprint detection device.

Abstract: A process for manufacturing an electronic device having an HV MOS transistor with a low multiplication coefficient and a high threshold in a non-implanted area of the substrate, this area having the same conductivity type and the same doping level as the substrate. The transistor is obtained by forming, over the non-implanted substrate area, a first gate region of semiconductor material having the same doping type as the non-implanted substrate area; and forming, inside the non-implanted substrate area, first source and drain regions of a second conductivity type, arranged at the sides of the first gate region. At the same time, a dual-gate HV MOS transistor is formed, the source and drain regions of which are housed in a tub formed in the substrate and having the first conductivity type, but at a higher concentration than the non-implanted substrate area. It is moreover possible to form a nonvolatile memory cell simultaneously in a second tub of the substrate of semiconductor material.

Abstract: A microactuator is attached to a first face of a coupling formed on a suspension, so that an R/W transducer projects from an opposite face. A hole in the coupling permits passage of an adhesive mass interposed between a rotor of the microactuator and the R/W transducer. A strip of adhesive material extends between a die accommodating the microactuator and the coupling, and externally surrounds the microactuator. The coupling acts as a protective shield for the microactuator, both mechanically and electrically. The coupling covers the microactuator at the front, and prevents foreign particles from blocking the microactuator. In addition, the coupling electrically insulates the R/W transducer, which is sensitive to magnetic fields, from regions of the microactuator biased to a high voltage. With the coupling, the strip forms a sealing structure, which in practice surrounds the microactuator on all sides.

Abstract: The present invention relates a circuit arrangement for the lowering of the threshold voltage of a diode configured transistor comprising a mirror transistor, a first transistor and a second transistor, said mirror transistor and said first transistor having in common the gate electrodes in a circuit node, said second transistor being connected in a transdiode configuration and placed between the gate electrode and the drain electrode of said first transistor, and a current source being connected to the gate electrode of said first transistor and to the drain electrode of said second transistor, characterized by comprising a third transistor which is configured to receive a switching signal at its gate electrode and is connected between the drain and the gate electrode of said first transistor.

Abstract: An internal addressing structure for a semiconductor memory with at least two memory banks, includes a counter associated for operation with each memory bank and capable of generating sequences of digital codes for addressing locations in the corresponding bank, a first circuit for causing a selective updating of the counters, a second circuit for loading into the counters a common initial digital code, forming part of an initial address supplied to the memory from the outside through an addressing line bus, corresponding to an initial memory location, and a third circuit capable of detecting a first signal, supplied to the memory from the outside and indicating the presence of a digital code on the bus, to cause the common initial digital code to be loaded into the counters.

Abstract: A voltage regulator includes a regulation MOS transistor and an amplifier providing an output for driving a gate of the regulation MOS transistor. The amplifier drives the gate based upon a difference between a reference voltage and a feedback voltage. The voltage regulator may further include a circuit for making the amplifier switch to a standby mode with low current consumption when the difference between the supply voltage and the output voltage of the regulator is below a first threshold. This is done while maintaining, at the gate of the regulation transistor, a voltage that keeps the regulation transistor on. The present invention is particularly applicable to the management of power supplies in portable telephones.

Abstract: A computer system including at least one central processing unit, a memory unit coupled to the at least one central processing unit, a set of watchpoints a set of watchpoints defined in the computer system, each watchpoint in the set of watchpoints including a programmable precondition register that stores a set of precondition codes, wherein the set of precondition codes is identical for each watchpoint in the set of watchpoints and a programmable action register that stores a set of action codes, wherein the set of action codes is identical for each watchpoint in the set of watchpoints, and a first comparator, having inputs coupled to the precondition register, that compares at least one precondition code in the set of precondition codes with a first data value in the computer system and provides a signal to the action register in response thereto. A method of triggering a watchpoint in a computer system is also provided.

Abstract: A digital decimation filter includes a set of cascaded integrator stages for generating a first signal comprised of bit words including a first number of bits as well as a set of cascaded derivative stages for receiving said first signal and generating therefrom an output comprised of bit words including a second number of bits. The second number of bits is smaller than said first number of bits and a bit discarding unit is located downstream of the integrator stages and upstream of the derivative stages for discarding a given number of least significant bits from the bit words of the first signal before this is received by the derivative stages. Said given number is defined as the difference between said first and said second number of bits.

Abstract: An integrated circuit capacitor includes a substrate, a first metal electrode on the substrate, and a dielectric layer on the first metal electrode. The dielectric layer includes a homogeneous combination of at least two dielectric materials having permittivities varying in an opposite way based upon an electric field, with a proportion of each dielectric material being chosen so that the integrated circuit capacitor has a desired voltage linearity. A second metal electrode is on the dielectric layer.

Abstract: A ballast compatible with different types of gas discharge lamps includes a power supply and a controller connected to the power supply. The controller includes a memory having a plurality of desired operating parameters stored therein for respective different types of gas discharge lamps. A sensing circuit causes the power supply to supply a current to the gas discharge lamp prior to start-up and senses a voltage based thereon indicative of a type of the gas discharge lamp. A control circuit causes the power supply to provide the desired operating parameters based upon the type of gas discharge lamp. Since the desired operating parameters are applied to the gas discharge lamp, the life of the lamp is increased.

Abstract: A structure and method for dissipating charges comprising an underlying dielectric layer disposed over capacitor plates of sensor circuitry a gap being formed conformally between adjacent plates and a topographic discharge grid over the underlying dielectric layer and wherein the topographic discharge grid fills at least a portion of the gap between the plates over the dielectric layer and diffuses electrostatic charges at the surface of the integrated circuit.

Abstract: The method of a protection circuit includes a reference voltage source and at least one circuit which are connected together via a switch. A memory element is connected to the input of the circuit, downstream of the switch. The switch is temporarily opened by a control signal generated by a monostable circuit when detecting switching of power elements belonging to an electronic device embedding the protection circuit. When the switch is open, the memory element supplies the circuit with the reference voltage previously stored. In this way, switching of the power element that might cause noise on the reference voltage cannot disturb the circuit and thereby cannot cause a faulty operation of the latter.

Abstract: A DC-DC converter may comprise a plurality of voltage multiplying stages of the capacitive type, each multiplying stage comprising a plurality of selectively connectable boosting branches. In one embodiment, the DC-DC converter comprises an inductor connected between a supply line and a ground line through a switching transistor; a voltage multiplying circuit formed by a plurality of voltage multiplying stages of capacitive type, connected together in cascade and each having an input connected to an intermediate node between the inductor and the transistor, and an output supplying a potential equal to the potential of the intermediate node multiplied by a respective multiplication factor. Each voltage multiplying stage comprises a plurality of parallel, selectively connectable boosting branches. The number of the active boosting branches may be varied in response to the energy required by the loads.