Abstract: A method for providing an SOI wafer that includes, on a wafer of monocrystalline semiconductor material, forming a hard mask of an oxidation-resistant material, defining first protective regions covering first portions of the wafer; excavating the second portions of the wafer, forming initial trenches extending between the first portions of the wafer; thermally oxidating the wafer, forming a sacrificial oxide layer extending at the lateral and base walls of the initial trenches, below the first protective regions; and wet etching the wafer, to completely remove the sacrificial oxide layer. Thereby, intermediate trenches are formed, the lateral walls of which are recessed with respect to the first protective regions. Subsequently, a second oxide layer is formed inside the intermediate trenches; a second silicon nitride layer is deposited; final trenches are produced; a buried oxide region is formed, and finally an epitaxial layer is grown.

Abstract: A flash EEPROM having an array of memory cells which include a common source line connecting together source electrodes of the memory cells. A resistive feedback element is coupled in series between the common source line and a positive potential when the memory cells must be electrically erased. The Flash EEPROM includes a voltage limiting circuit coupled to the common source line for limiting the potential of the common source line to be prescribed maximum value lower than the positive potential.

Abstract: An indium-implanted transistor is provided. The transistor has a silicon channel region that includes a buried layer of an Si1−xGex alloy into which indium is implanted, with 10−5≦x≦4×10−1. A first method for fabricating an indium-implanted transistor is also provided. A multilayer composite film is produced on at least one region of a surface of a silicon substrate where a channel region of the transistor is to be formed. The multilayer composite film includes at least one Si1−xGex alloy layer, in which 10−5≦x≦4×10−1, and an external silicon layer. Indium is implanted into the Si1−xGex alloy layer, and fabrication of the transistor is completed so as to produce the transistor with a channel region that includes a buried Si1−xGex alloy layer. Additionally, a second method for fabricating an indium-implanted transistor is provided.

Abstract: A method for fabricating a silicon-on-insulator (SOI) wafer that includes a monocrystalline silicon substrate with a doped region buried therein is provided. The method includes forming a plurality of trench-like openings extending from a surface of the substrate to the doped buried region, and selectively etching through the plurality of trench-like openings to change the doped buried region into a porous silicon region. The porous silicon region is oxidized to obtain an insulating region for the SOI wafer.

Abstract: A column decoder circuit for page reading of a semiconductor memory includes a first level decoder stage, a second level decoder stage, and a plurality of bit selection stages, each comprising a plurality of selection branches; wherein each selection branch is connected to a respective input of a multiplexer and has a plurality of first level selector stages and a second level selector stage. Each second level selector stage comprises a first addressing selector for addressing a first group of bit lines. Each bit selection stage further comprises a second addressing selector for addressing a second group of bit lines, current and next page selectors for selecting one of the first and second groups of bit lines.

Abstract: The present invention relates to a one-time programmable (OTP) device including three fuses connected in parallel to a logic element which determines that the device is programmed when at least one of the fuses open. The present invention comprises a one-time programmable device that, before the one-time programmable device is programmed, provides, in response to a test signal, a simulation output signal that simulates an output signal that the one-time programmable device provides if the one-time programmable device is programmed.

Abstract: A method of manufacturing a bipolar transistor in an N-type semiconductor substrate, including the steps of depositing a first base contact polysilicon layer and doping it; depositing a second silicon oxide layer; forming in the first and second layers an opening; annealing to form a third thin oxide layer and harden the second oxide layer; implanting a P-type dopant; depositing a fourth silicon nitride layer; depositing a fifth silicon oxide layer and etching it; anisotropically etching the fifth, fourth, and third layers; performing cleanings during which the fifth layer is reetched and takes a flared profile; depositing a sixth polysilicon layer; and implanting an N-type dopant.

Abstract: Presented is an analog voltage value measuring device for measuring any of a set of voltage references that are generated inside a memory architecture. The selected voltage to be measured is connected to a facility line through a multiplexer. The memory architecture includes a set of output buffers connected to a respective set of output pads. The device also includes a converter block, connected between the facility line and the output buffers of the memory architecture for converting a measured analog value of a voltage reference selected by the multiplexer to a digital value, which is presented on the output pads. A method of measuring an analog voltage value in a memory device is also disclosed. The method includes selecting an analog voltage value from the set of voltage values; transferring the selected analog value onto the facility line; converting the selected analog value to a digital value; and presenting the digital value on the output pads.

Abstract: A circuit structure for programming data in reference cells of an electrically programmable/erasable integrated non-volatile memory device includes a matrix of multi-level memory cells and a corresponding reference cell provided for comparison with a respective memory cell during the read phase. The reference cell is incorporated, along with other cells of the same type, in a reference cell sub-matrix which is structurally independent of the memory cell matrix and directly accessed from outside in the DMA mode. The bit lines of the sub-matrix branch off to a series of switches which are individually operated by respective control signals REF(i) issued from a logic circuit with the purpose of selectively connecting the bit lines to a single external I/O terminal through a single addressing line of the access DMA mode.

Abstract: An integrated self-powered and switching electronic circuit regulates a stable reference voltage and comprises a band-gap voltage generator to produce said stable reference voltage for a system circuit block that is generally supplied by the output of the band-gap generator through a comparator and an error amplifier. A regulating loop is provided between the output of the system block and the input of the voltage generator circuit to supply a voltage signal produced by the output of the system block. Advantageously, the voltage generator circuit incorporates both the comparator and the error amplifier.

Abstract: A filtering circuit includes circuits for delivering first and second ramp-shaped signals when a logic signal to be filtered changes values, and includes logic circuits each with a switching threshold, for receiving the ramp-shaped signals. A memory unit delivers an output signal having a first value when outputs of the logic circuits have a first pair of values, and delivers a second value when the outputs of the logic circuits have a second pair of values. The filtering circuit may be applied to the filtering of an external clock signal in serial type memory devices.

Abstract: The device and method monitor the current delivered to a load through a power transistor including a sense transistor. The circuit includes a disturbances attenuating circuit that has a differential stage, and first, second and third stages referenced to ground, the respective input nodes of which are connected in common to an output node of the differential stage. The third stage is formed by a transistor identical to a transistor of the first stage and delivers a current signal through a current terminal thereof, proportional to the current being delivered to the load.

Abstract: An analog-to-digital converter including a first module of the type having a series of processor stages, each of the stages performing two conversions of the signal output by the preceding stage, firstly an analog-to-digital conversion and secondly a digital-to-analog conversion, followed by subtracting the signal obtained from the output signal of the preceding stage to provide the analog output signal of the stage. The first module further assembles together the signals digitized by each stage (S1, . . . , Si) so as to provide an assembled digital signal (SN(nT) which represents the input signal (e(nT) of the converter in digital form.

Abstract: There is disclosed a cache memory for use in a data processor. The cache memory comprises a first static random access memory (SRAM) that receives up to N incoming bytes of data on an input bus and that stores the up to N incoming bytes of data in an N-byte addressable location. M incoming bytes of data may be written in each of the N-byte addressable locations during a write operation (where M may be less than N) and the M written bytes of data and N−M unwritten bytes of data are output from each N-byte addressable location on an output bus of the first SRAM during each write operation. The cache memory also comprises a parity generator coupled to the first SRAM that receives the M written bytes of data and the N−M unwritten bytes of data and generates at least one write parity bit associated with the M written bytes of data and the N−M unwritten bytes of data.

Abstract: A transconductance stage includes at least one principal bipolar transistor having a base linked to an input terminal, a collector linked to an output terminal, and an emitter linked to a supply terminal through a resistor. At least one bipolar compensation transistor is connected in parallel to the principal transistor and linked without going through the resistor to the supply terminal. The value RE of the resistance is chosen so that RE*I0>VT/2, where VT is the thermal voltage and I0 is the quiescent current of the principal transistor.

Abstract: A MOS transistor with a drain extension includes an isolation block on the upper surface of a semiconductor substrate. The isolation block has a first sidewall next to the gate of the transistor, and a second sidewall that is substantially parallel to the first sidewall. The isolation block further includes a drain extension zone in the substrate under the isolation block, and a drain region in contact with the drain extension zone. The drain region is in the substrate but is not covered by the isolation block.

Abstract: A driving circuit of a DC motor includes a control circuit for providing a control signal, and a motor drive circuit commanded by the control circuit for providing respective command signals for the switches of an output power stage connected to the DC motor. The output power stage is connected to a power supply line and drives the windings of the DC motor. The driving circuit prevents generation of voltage surges having a significant magnitude on the power supply line because the driving circuit has logic circuits for preventing any substantial inversion in the direction of current flow in the supply lines when the DC motor operates as a current generator.

Abstract: An integrated memory location structure includes an isolated semiconductor layer between the source region and the drain region of a transistor, and between the channel region and the control gate of the transistor. The isolated semiconductor layer includes two potential well zones separated by a potential barrier zone under the control gate of the transistor. A write circuit biases the memory location structure to confine charge carriers selectively in one of the two potential well zones. A read circuit biases the memory location structure to measure the drain current of the transistor and determine therefrom the stored logic state imposed by the position of the charges in one of the potential well zones.

Abstract: A power device with integrated voltage stabilizing circuit, comprising a MOS transistor that is connected in parallel to a circuit that is integrated in a power device, at least one Zener diode with a series-connected resistor being connected in parallel to the transistor, the gate terminal of the transistor being connected to an intermediate node between the Zener diode and the resistor, the anode terminal of the Zener diode and the drain terminal of the transistor being connected to an input voltage of the circuit.

Abstract: A method manages lamp fault conditions in electronic ballasts for one or more gas discharge lamps. The method for fault management of electronic ballast for at least one gas discharge lamp includes the steps of: preheating the lamp filaments applying a low current for a predetermined time; igniting the lamp by increasing at a predetermined rate the voltage applied up to a predetermined strike value; monitoring the lamp current; repeating the steps of igniting the lamp and monitoring the lamp current for a predetermined numbers of times if the lamp current is over a predetermined threshold; and powering the lamp at normal operating conditions.