Abstract: A system for reducing the number of programmable architecture elements in a look-up table required for implementing Boolean functions or operations that are identical or logically equivalent is provided. The system may include a single set of storage elements connected to the inputs of multiple decoders, and the storage elements may be concurrently accessed by the decoders to provide simultaneous multiple outputs thereto.

Abstract: The present invention relates to a method and a circuit using the method thereof for minimising the phase errors during the driving of an electric motor, and a circuit using the method thereof, having a stator winding, a permanent magnet rotor assembly, and devices able to sense a rotor position, which comprises the following steps: a) generating of a rotor position signal (10, 14, 39), by means of said devices able to sense said rotor position; b) detecting at least two information from at least two edges (11, 12; 15, 16) of said rotor position signal (10, 14, 39) inside a measure period; c) generating a driving signal (9, 13, 38), in finction of said at least two information (11, 12; 15, 16) inside the measure period, so as to follow the rotor velocity.

Abstract: The gyroscope is formed by a driving system including a driving mass having an open concave shape; an accelerometer including a sensing mass and comprising mobile sensing electrodes; a linkage connecting the driving mass to the sensing mass. The sensing mass is surrounded on three sides by the driving mass and has a peripheral portion not facing the sensing mass. The mobile sensing electrodes extend integral with the sensing mass from the peripheral portion not facing the driving mass and are interleaved with fixed sensing electrodes. Thereby, there are no passing electrical connections extending below the sensing mass. Moreover the linkage includes springs placed equidistant from the center of gravity of the accelerometer, and the gyroscope is anchored to the substrate with anchoring springs placed equidistant from the center of gravity of the assembly formed by the driving system and by the accelerometer.

Abstract: Sensing circuitry for reading and verifying the contents of electrically programmable and erasable non-volatile memory cells, comprises a sense amplifier having a first sensing circuit portion connected to a cell to be read and provided with an output terminal for connection to a first input terminal of a comparator, and having a second reference circuit portion connected to a reference current generator and provided with an output terminal for connection to a second input terminal of said comparator, characterized in that said first and said second circuit portions comprise a series of first and second transistors, respectively, being connected between a first voltage reference and a second voltage reference and having respective points of interconnection connected to said output terminals of said first and second circuit portions.

Abstract: A method is for generating a key from the fixed pattern noise (FPN) of a CMOS image sensor to be used in generating a digital authentication signature. The key may be generated by temporarily disabling the FPN cancellation circuit that is conventionally included in the system, and generating a substantially “black” image to produce a digitized FPN signal. The key may then be generated from characteristics of the FPN, such as by comparing pairs of pixels, for example.

Abstract: The circuit for generating reference voltages for reading a multilevel memory cell includes the following: a first memory cell and a second memory cell respectively having a first reference programming level and a second reference programming level; a first reference circuit and a second reference circuit respectively connected to said first and said second memory cells and having respective output terminals which respectively supply a first reference voltage and a second reference voltage; and a voltage divider having a first connection node and a second connection node respectively connected to the output terminals of the first reference circuit and of the second reference circuit to receive, respectively, the first reference voltage and the second reference voltage, and a plurality of intermediate nodes supplying respective third reference voltages at equal distances apart.

Abstract: A method enhances selectivity between a film of a light-sensitive material and a layer to be subjected to etching in the course of fabrication processes of an electronic semiconductor device starting from a semiconductor material wafer. The method includes radiating the wafer with an ion beam subsequently to depositing the layer to be etched and defining a circuit pattern on the film of light-sensitive material. An alternative method exposes the wafer to a non-reactive gas medium under plasma rather than radiating the wafer with an ion beam.

Abstract: A content addressable memory (CAM) includes a voltage power supply input and an enable input. An enable control circuit is connected to the enable input, and operates to compare an external voltage to an enable reference voltage. If the external voltage drops below the enable reference voltage, the enable control circuit drives the enable input to place the CAM into a low current, stand-by mode of operation. A voltage supply back-up circuit is connected to the voltage power supply input, and operates to compare the external voltage to a supply reference voltage. If the external voltage drops below the supply reference voltage, the voltage supply back-up circuit switches the voltage power supply input for the CAM from the external voltage input to a battery back-up. As an alternative, the voltage power supply input for the CAM includes a separate power input for a CAM array, and the switch causes only that separate power input for the CAM array to be powered from the battery back-up.

Abstract: A read and analog-to-digital data conversion channel includes an input circuit receiving an input data stream, and a time interleaved analog-to-digital converter connected to the input circuit. The time interleaved analog-to-digital converter includes a pair of analog-to-digital converters functioning in parallel and at half the clock frequency. A signal path through the time interleaved analog-to-digital converter is subdivided into two parallel paths through the pair of analog-to-digital converters. There is a first path for even bits and a second path for odd bits. A digital post-processing circuit is connected to the two parallel paths of the time interleaved analog-to-digital converter, and has an output providing a reconstructed data stream. At least one adjusting digital-to-analog converter is connected between the digital post-processing circuit and the input circuit for control thereof.

Abstract: A system with chrominance delay lines has a first sampled channel including at least one smoothing filter, and has a second unsampled channel. A continuous bypass filter is placed in the second channel to balance the pulse response from these two channels.

Abstract: An electronic power device is integrated monolithically in a semiconductor substrate. The device includes a power region, itself having at least one P/N junction provided therein which comprises a first semiconductor region with a first type of conductivity extending into the substrate from the top surface of the device and being diffused into a second semiconductor region with the opposite conductivity from the first; and an edge protection structure of substantial thickness and limited planar size incorporating at least one trench filled with dielectric material.

Abstract: The present invention refers to a fully differential operational amplifier of the folded cascode type. In one embodiment the fully differential operational amplifier comprises: a differential input stage able to drive a differential output stage; said differential output stage includes a first branch having at least a first and a second transistor, and a second branch having at least a third and a fourth transistor; said first and second branch are coupled to a first and a second voltage source; a feedback circuit of said first, second, third and fourth transistors that is constituted by a single amplifier having four inputs and four outputs, said four inputs taking the voltages present on a terminal of said first, second, third and fourth transistors, and providing voltages to the control elements of said first, second, third and fourth transistors, which voltages depend on the input voltages of said four inputs.

Abstract: This invention is directed to a method of making a capacitive distance sensor that includes one or more sensor cells each with first and second capacitor plates. The method includes determining an expected range of sizes of objects the sensor will be used to detect and determining a total perimeter value for each of a plurality of capacitor patterns. Each capacitor pattern includes a different arrangement of the first and second capacitor plates and the total perimeter value is the sum of the perimeter values for the first and second capacitor plates. The method selects one of the capacitor patterns based on the expected size of the object and on the total perimeter values determined for the capacitor patterns. The selecting step includes selecting whichever one of the capacitor patterns has the largest total perimeter value if the object is smaller than each of the one or more sensor cells.

Abstract: A method is provided for fabricating a semiconductor device having a gate-all-around architecture. A substrate is produced so as to include an active central region with an active main surface surrounded by an insulating peripheral region with an insulating main surface. The active main surface and the insulating main surface are coextensive and constitute a main surface of the substrate. A fist layer of Ge or an SiGe alloy is formed on the active main surface, and a silicon layer is formed on the first layer and on the insulating main surface. The silicon layer and the first layer are masked and etched in order to form a stack on the active main surface, and the first layer is removed so that the silicon layer of the stack forms a bridge structure over the active main surface. The bridge structure defines a tunnel with a corresponding part of the active main surface.

Abstract: A circuit for modifying a clock pulse train is described. The circuit has an input for receiving the clock pulse train, a first logic circuit having an output which is responsive to a clock pulse edge of a first polarity and a second logic circuit having an output which is responsive to a clock pulse edge of a second polarity. A two input multiplexer is provided to receive respectively the outputs of the first and second logic circuits and is arranged to provide an output representing a modification of the input clock pulse train.

Abstract: A method for controlling a vehicle semi-active suspension system comprising at least one suspension, providing for: detecting vehicle dynamic quantities during the vehicle ride; using the detected dynamic quantities, determining an index of ride comfort and an index of roadholding; applying a weight factor to the index of ride comfort and to the index of roadholding and, based on a Sky Hook control model, determining a target damping force characteristics for the at least one suspension of the suspension system; controlling the at least one suspension to put the respective damping force characteristics in accordance with the calculated target damping force characteristics. The weight factor is calculated dynamically during the vehicle ride, by means of a fuzzy calculation on the detected vehicle dynamic quantities.

Abstract: An electronic power device is integrated on a semiconductor substrate having a first conductivity type, on which an epitaxial layer of the same conductivity type is grown. The power device comprises a power stage and a control stage, this latter enclosed in an isolated region having a second conductivity type. The power stage comprises a first buried area having the second conductivity type and a second buried area, partially overlapping the first buried area and having the first conductivity type. The control stage comprises a third buried area, having the second conductivity type, and a fourth buried area, partially overlapped to the third buried area and having the first conductivity type. Said first, second, third and fourth buried areas are formed in the epitaxial layers at a depth sufficient to allow the power stage and the control stage to be entirely formed in the epitaxial layer.

Abstract: A process and a system is described for generating an MPEG output bitstream starting from an MPEG input bitstream. The output bitstream has a resolution modified with respect to the resolution of the input bitstream. -In the input bitstream, first portions that substantially do not affect and second portions that do affect resolution variation are distinguished. The second portions are then subjected to a function of modification of the resolution obtained by filtering the second portions in a domain of the discrete cosine transform, and then are transferred to the output bitstream. A corresponding computer program product is also provided.

Abstract: A method of illuminating a layer of a material, in particular a photosensitive resin, using a light source, in order to expose an area of that material to a useful dose of light for subsequent etching of that material in that area, consisting in effecting a first exposure through a pattern of a first mask made up of a central hole and peripheral holes with a first dose of light less than said useful dose, and a second exposure through a pattern of a second mask made up of a single hole with a second dose of light such that the cumulative total of said first dose induced through the central hole of the first mask and the second dose induced through the single hole of said second mask produces at least said useful dose over said area.

Abstract: Described herein is an asynchronous serial dichotomic sense amplifier comprising a first comparator stage having a first input receiving the cell current flowing in the multilevel memory cell, the content of which is to be read, a second input receiving a first reference current, and an output supplying the first of the bits stored in the multilevel memory cell; a multiplexer stage having a selection input connected to the output of the first comparator stage, a first signal input receiving a second reference current, a second signal input receiving a third reference current, and a signal output selectively connectable to the first or the second signal input depending on the logic level present on the selection input; and a second comparator stage having a first input receiving the cell current, a second input connected to the signal output of the multiplexer stage, and an output supplying the second of the bits stored in the multilevel memory cell.