Abstract: A bus interface unit includes a random-access transaction buffer and at least one pointer queue. The transaction buffer stores entries for both in-order transactions and combinable write transactions, and the pointer queue stores pointers to the buffer entries for in-order transactions so as to order the in-order transactions. When a received combinable write transaction has a writing address that falls within the address range of a stored combinable write transactions, the received transaction is merged with the stored transaction. Additionally, a method is provided for processing requested bus transactions. The bus interface unit determines if a requested transaction is a combinable write transaction. If not, address and data information for the requested transaction is loaded into an empty entry in a random-access buffer, and a pointer to that buffer entry is placed in a pointer queue.

Abstract: An operating voltage selection circuit for non-volatile semiconductor memories, comprising: means (1) for reading at least one one-time programmable non-volatile memory cell (10), suitable to generate a signal (LV) which indicates the requested type of operating voltage of a non-volatile memory, which depends on the programmed or non-programmed state of the memory cell; memory enabling means (5), which comprise an inverter (30, 31) and are provided with means (32) for modifying the switching threshold of the inverter as a function of the signal that indicates the requested type of operating voltage; output means (2), which are connected to means for sensing data of the memory and to output terminals of the memory, comprising a CMOS inverter (20, 50) and means (23) for modifying the output current of the inverter as a function of the signal (LV) for indicating the requested type of operating voltage; and means (8) for the internal synchronization of the memory, which comprise pluralities of transistors (40, 41

Abstract: Silver interconnects are formed by etching deep grooves into an insulating layer over the contact regions, exposing portions of the contact regions and defining the interconnects. The grooves are etched with a truncated V- or U-shape, wider at the top than at any other vertical location, and have a minimum width of 0.25 .mu.m or less. An optional adhesion layer and a barrier layer are sputtered onto surfaces of the groove, including the sidewalls, followed by sputter deposition of a seed layer. Where aluminum is employed as the seed layer, a zincating process may then be optionally employed to promote adhesion of silver to the seed layer. The groove is then filled with silver by plating in a silver solution, or with silver and copper by plating in a copper solution followed by plating in a silver solution.

Abstract: A voltage regulator for memory circuits has a differential stage having a non-inverting input terminal receiving a control voltage independent of the temperature; an inverting input terminal connected to a ground voltage reference; a feed terminal connected to a booster circuit adapted for producing a boosted voltage; and an output terminal connected to an output terminal of the voltage regulator, for producing an output voltage reference starting from the comparison of input voltages. The voltage regulator further comprises a connecting transistor inserted between the feed terminal and the output terminal of the differential stage, the connecting transistor being source follower having a control terminal connected to the output terminal of the differential stage, as well as a source terminal connected to the output terminal of the voltage regulator, in such a way as to self-limit the transition of the voltage on the output terminal.

Abstract: A low noise integrated differential AC amplifier includes a cascode differential input stage comprising first and second branches. The first branch includes a first input transistor and the second branch includes a second input transistor. Each transistor has a collector and an emitter, and the emitters being connected together to define a common emitter node. The amplifier also includes two output stages connected to respective outputs of the first and second branches. Each output stage may include a common collector transistor stage including a bias current generator and a feedback circuit. A first biasing circuit forces a first biasing current through the first input transistor by injecting the first biasing current on the collector thereof. A second biasing circuit forces a second biasing current through the first input transistor by injecting the second biasing current on the collector thereof.

Abstract: A semiconductor device includes a chip forming an integrated circuit; a connection substrate; an internal coupling mechanism; and at least one optical communication system. The connection substrate comprises an external coupling mechanism for electrically coupling to a device other than the chip. The internal coupling mechanism electrically couples the integrated circuit to the external coupling mechanism. The at least one optical communication system comprises two optoelectronic parts. The first optoelectronic part is either an emitter or a receiver which is integrated into the chip and constitutes one component of the integrated circuit. The second optoelectronic part is borne by the connection substrate and is able to be externally connected to the connection substrate. The second optoelectronic part faces the first optoelectronic part and is capable of exchanging light signals with the first optoelectronic part.

Abstract: A semiconductor device includes first through fourth pads and first through third external connection leads, with the first external connection lead being a ground connection lead and the first and second pads being ground pads. First through fourth connection wires selectively connect the pads to the external connection leads. Additionally, a first ground line is connected to the first pad, a second ground line is connected to the second pad, a first protective diode connects the first ground line to the third pad, and a second protective diode connects the second ground line to the fourth pad. The first external connection lead is connected to the first pad via the first connection wire and to the second pad via the second connection wire, the third connection wire connects the third pad to the second external connection lead, and the fourth connection wire connects the fourth pad to the third external connection lead.

Abstract: A method and circuit for testing a packaged semiconductor memory device allow the acquisition of information on redundant elements by performing one of three possible redundancy rollcall tests on the packaged memory chip. By stimulating the packaged device's pins, the memory chip is set in one of the three test modes. In the first test mode, a preset signal indicating redundancy is sensed and the state of an output pin is changed. In the second test mode, memory array rows are sequentially addressed and the state of an output pin is changed when a redundant row is addressed. In the third test, array columns are sequentially addressed and, when a redundant column is addressed, the state of the output pin to which the redundant column is mapped is changed.

Abstract: The device permits selection between two design options of an integrated circuit by causing a corresponding circuit unit of the integrated circuit to adopt one of two possible different operative states. More specifically, the device provides an inverter, of which the output terminal is connected to the control terminal of the circuit unit and the input terminal is connected to first and second supply terminals, via a conductor and a capacitor, respectively. The conductor can be broken by means outside the integrated circuit, and the capacitor is connected in parallel with a diode connected for reverse conduction. The device does not require control signals, takes up a very small area, has practically zero consumption, and can be formed in unlimited numbers on the same integrated circuit.

Abstract: A driver circuit for slope-controlled pulsed switching of a load having a MOS switching transistor switching the load and a control loop with an amplifier having an amplifier input coupled with a switch control pulse source, an amplifier output connected with the gate of the MOS switching transistor, and a feedback capacitor. The driver circuit also includes a switchable current mirror circuit with a current mirror transistor formed by the MOS switching transistor and a diode transistor wired as a current mirror diode, a connection point between the diode transistor and the gate of the MOS switching transistor being connected with the amplifier output. A timer circuit is supplied on the input side with the switch control pulses from the switch control pulse source, and switches the diode transistor into a conductive state for essentially the duration of each switch control pulse edge and otherwise into a nonconductive state.

Abstract: A multi-level memory circuit for binary information includes a plurality of memory cells each adapted to store more than one item of binary information, and each memory cell includes at least one floating gate MOS transistor. The information stored therein corresponds to the level of the cell threshold voltage. A read voltage generating circuit is adapted to an input supply voltage and provides a read voltage to the memory cells. The read voltage generating circuit includes a voltage boosting circuit providing the read voltage greater than the input supply voltage.

Abstract: A circuit for selectively enabling one circuit from among a plurality of circuit alternatives of an integrated circuit includes a selection circuit for selecting one circuit from among the plurality of circuit alternatives. The selection circuit is controlled by a bistable circuit having a preferred state. A disactivatable forcing circuit associated with the bistable circuit is provided for forcing the bistable circuit into a state opposite than the preferred state, so that when the forcing circuit is disactivated, the bistable circuit automatically switches to the preferred state.

Abstract: A read circuit for non-volatile memories having an array section, with a corresponding bitline, and a reference section, with a corresponding reference bitline. A differential amplifier for comparing voltage signals obtained by current/voltage conversion of a current signal of an array cell and of a reference current signal is connected to the respective bit lines. A cascode transistor for each one of the array and reference sections, each driven by a NOR logic gate; a charge transistor for the bitline and a charge transistor for the reference bitline; column decoding transistors for the array section and for the reference section; the circuit further comprising an additional transistor which is connected between the NOR gate of the array side and a node for acquiring the array voltage sent to the differential amplifier, the additional transistor increasing the speed of the process for reading the bitline when the bitline is not charged.

Abstract: A method is provided for patterning a submicron semiconductor layer of an integrated circuit, and an integrated circuit formed according to the same. An interlevel dielectric layer is formed over the surface of the integrated circuit. A planarizing layer is formed over the interlevel dielectric layer. A photoresist layer is formed and patterned over the planarizing layer. The planarizing layer is etched to form openings exposing selected portions of the interlevel dielectric layer, wherein each opening has the same lateral dimensions. The photoresist and planarizing layers are then removed. The interlevel dielectric layer is etched in the openings to expose portions of the underlying integrated circuit.

Abstract: A device for extracting parameters for decoding a video data flow, contained in headers preceded by a starting code of series of data coded according to an MPEG standard, organized, independently and according to the starting code, and storage of the parameters in three register banks.

Abstract: A dividing circuit comprises, connected in a ring, a plurality M of transistor stages, where M is an even integer. Each transistor stage comprises an input node, a clock node and an output node. A tri-state inverter stage has an input node connected to the output node of a preceding transistor stage in the ring, an enable node connected to the clock nodes of the transistor stages, and an output node connected to the input node of a subsequent transistor stage in the ring.

Abstract: A method for the testing of the retention time of a piece of information in a dynamic memory cell includes increasing the leakages of current in this cell to accelerate the loss of information. Under these testing conditions, a reduced retention time is controlled to approach the true retention time obtained under conditions of normal reading. This method makes it possible to reduce the time taken to test the retention time of the dynamic memories while at the same time being very reliable.

Abstract: A multi-level memory circuit for binary information includes a plurality of memory cells each adapted to store more than one item of binary information, and each memory cell includes at least one floating gate MOS transistor. The information stored therein corresponds to the level of the cell threshold voltage. A write signal generating circuit is adapted to an input supply voltage and provides a write voltage to the memory cells. The write signal generating circuit generates internally at least one write voltage having a selectable or selected value from a number of discrete regulated values corresponding to the number of the discrete levels provided.

Abstract: A method and data structure for a header-formatted defective sector management system. A spare sector is allocated for each n sectors. When a defective one of the n sectors is identified, the sectors are slipped using the spare sector. The location of the defective sector and the type of defect, e.g., data field or header field, is indicated by a data structure written to the header field of at least one of the non-defective sectors. When a second defective sector is identified, the system operates to disposition the second defective sector based on the type of the first defective sector. If the first defective sector was a defect in the data field and the second defective sector is a defect in the header field then the first defective sector is converted to a reassigned sector and the second defective sector is slipped. This avoids the problem of reassigning a sector having a defective header field.

Abstract: A device including a mechanism (4) for generating a counting clock signal (CKM) whose frequency is less than or equal to n times twice the transmission frequency. The device also includes a detection mechanism (10) for detecting the transitions (TD) of the signal (DS) at the counting frequency and for delivering corresponding detection signals (ST), a selection mechanism (2) for receiving each detection signal (ST) and for delivering or otherwise a selection signal (RS) depending on the satisfying or otherwise of a predetermined selection criterion, and a frequency divider-by-n (30) which receives the counting clock signal, in order to sample the carrier signal after a predetermined time delay (Tr) after each detected transition. Provided are a sampling control device and method which are completely digital and therefore use no analog component of the phase-locked loop type and are very simple to produce at an industrially economical cost.