Abstract: A method and apparatus for performing head switch operations in a magnetic disk system with a magnetic disk device that is segmented into a plurality of cylinders. The cylinders are grouped into an inner zone, a middle zone, and an outer zone. The inner zone is near the innermost area of the magnetic disk device. The outer zone is near the outermost area of the magnetic disk device. The middle zone is in between the inner zone and the outer zone. The head switch is performed from a current head at a current cylinder to a target head at a target cylinder. Prior to the head switch, the system determines if the current cylinder is in either the inner zone or the outer zone. If the current cylinder is in either the inner zone or the outer zone, then the system determines if the target cylinder is in either the inner zone or the outer zone. If the target cylinder is in either the inner zone or the outer zone, then the system seeks the current head to the middle zone and then performs the head switch.

Abstract: Switching circuit comprising a reference voltage, an input voltage, suitable to assume alternatively a negative value or a value equal to said reference voltage, an output node, suitable to assume selectively three possible voltage values equal to a supply voltage, to the reference voltage, to the input voltage or, alternatively, to be kept floating, in response to a first, a second, a third, a fourth, a fifth, a sixth control logic signal, switching between the supply voltage and the reference voltage.

Abstract: A floating-gate type memory uses voltages that are low in terms of absolute value with a reliable and compact word selection device. The device is compatible with Flash-EEPROM type memories. An N type well transistor is used as a word selection transistor.

Abstract: The present invention relates to a power output stage for the control of plasma screen cells. It includes VDMOS-type N-channel charge and discharge transistors, the charge transistor being arranged to form a compound P-channel transistor. These transistors enable to issue a charge current to an output and to absorb a discharge current from this output. Two inverters are sized so that the potential of the control gate of the charge transistor drops more rapidly than the output potential when a discharge of this output is controlled. Thus, an output stage of limited bulk and without any risk of simultaneous conduction of the charge and discharge transistors is implemented.

Abstract: The process provides first for the accomplishment of low-doping body regions at the sides and under a gate region and then the accomplishment of high-doping body regions inside said low-doping body regions and self-aligned with said gate region. There is thus obtained an MOS power transistor with vertical current flow which has high-doping body regions self-aligned with said gate region and with a reduced junction depth.

Abstract: A dual landing pad structure is formed with a dielectric pocket. A first opening is formed through a first dielectric layer to expose a portion of a diffused region. A first polysilicon landing pad is formed over the first dielectric layer and in the opening. This landing pad will provide for smaller geometries and meet stringent design rules such as that for contact space to gate. A dielectric pocket is formed over the polysilicon landing pad over the active region. A second conductive landing pad is formed over the polysilicon landing pad and the dielectric pocket. A second dielectric layer is formed over the landing pad having a second opening therethrough exposing a portion of the landing pad. A conductive contact, such as aluminum, is formed in the second contact opening. The conductive contact will electrically connect with the diffused region through the landing pad. Misalignment of the conductive contact opening over the landing pad may be tolerated without invading design rules.

Abstract: A circuit switches a capacitive value in an exclusive manner to a selected integrated amplifier among a plurality of integrated amplifiers. The circuit includes a first current generator connected between a first supply node and a first node of the circuit, and a second current generator connected between a second supply node and a second node of the circuit. The second current generator is electrically in parallel with the capacitor. An array of switches equal in number to the integrated amplifiers are exclusively switched ON for connecting a directly biased diode between the first node and the second node. Each integrated amplifier has a supply node coupled to a connecting node between a respective diode and a respective connecting switch of the array of switches.

Abstract: A method and integrated circuit for providing drive signals to a polyphase dc motor. The integrated circuit is fabricated on a semiconductor substrate for providing drive signals to a polyphase dc motor. The circuit includes a coil drive circuit for connection to drive coils of the motor to selectively supply drive currents thereto in a predetermined sequence. A sequencer circuit commutatively selects the drive coils to which the drive currents are selectively supplied, and a motor, speed controlling circuit controls the speed of the motor by controlling the speed of commutation. A temperature sensing element, such as a diode, is fabricated in the substrate to indicate the temperature of the substrate, and a temperature measuring circuit is connected to the temperature sensing element and to the motor speed controlling circuit to operate the motor speed controlling circuit to slow the speed of the motor when the temperature of the substrate exceeds a first predetermined temperature.

Abstract: A programmable non-volatile memory device has a plurality of rows of memory cells that are accessible through selection addresses, with the number of physical rows being greater than the number of rows that are addressable at a given time. An associating circuit associates selected physical rows of the memory device with selection addresses. The associating circuit includes an associative memory that has a programmable memory location for each physical row of the memory device, and each memory location in the associative memory has an address field and at least one state bit. In one preferred embodiment, in the read mode, a row of the memory device is selected when the corresponding memory location in the associative memory contains the received address and state bits indicating that the row stores valid data for the received address. A method of programming such a non-volatile memory device is also provided.

Abstract: A high-voltage lateral MOSFET transistor structure constituted by various interdigitated modular elements formed on a layer of monocrystaline silicon is described together with a process for its fabrication.To save area of silicon and to reduce the specific resistivity RDS on doping drain regions are formed by implanting doping material in the silicon through apertures in the field oxide obtained with a selective anisotropic etching by utilizing as a mask the strips of polycrystaline silicon which serve as gate electrodes and field electrodes.

Abstract: A static sense amplifier, particularly for non-volatile memories, is disclosed. The static sense amplifier includes a differential stage having non-inverting and inverting input terminals respectively connected to a reference branch and to a matrix branch of a matrix of memory cells, and a feedback loop coupled between the output of the differential stage and the inverting input terminal thereof. The feedback loop includes a pull-up device having a control terminal driven by the output of the differential stage and a terminal connected to the inverting input terminal of the differential stage.

Abstract: The row decoder includes a predecoding stage supplied with row addresses and generating predecoding signals; and a final decoding stage, which, on the basis of the predecoding signals, drives the individual rows in the array. The predecoding stage includes a number of predecoding circuits presenting two parallel signal paths: a low-voltage path used in read mode, and a high-voltage path used in programming mode. A CMOS switch separates the two paths, is driven by high voltage via a voltage shifter in programming mode, and, being formed at predecoding level, involves no integration problems.

Abstract: A BEMF detector and method detect the BEMF of a three-phase motor using a fully differential detection system. The motor has a first coil coupled between a first coil tap and a center tap, a second coil coupled between a second coil tap and the center tap, and a third coil coupled between a third coil tap and the center tap. The BEMF detector includes a differential amplifier having first and second inputs and first and second outputs, with the first input being coupled to one of the coil taps and the second input being coupled to the center tap. The BEMF detector also includes a comparator having first and second inputs coupled respectively to the first and second outputs of the differential amplifier and an output at which a BEMF signal is produced that is related to the BEMF of the motor. The differential amplifier may be part of an anti-alias filter structured to fix to a known stable value a common mode at the outputs of the differential amplifier.

Abstract: A synchronous counter circuit having a plurality of bit counting stages, each corresponding to a bit position for representing counts, from a least significant bit to a most significant bit. Each bit counting stage includes a flip-flip circuit and a synchronization circuit and each includes circuitry for receiving a pulse train clock signal, synchronously counting said clock signal and outputting an output bit signal corresponding to said counters' stage bit position. The bit counting stages are arranged in two groups, a reset group and a counting group, such that the output bit signal of said flip-flop circuit of the reset group synchronizes data propagation between each bit counting stage of the counting group.

Abstract: A device in an emitter-switching configuration comprises a high-voltage transistor having a first terminal connected directly to a first power terminal of the device, a control terminal connected to a control terminal of the device, and a second terminal. The device also includes a low-voltage transistor having a first terminal connected directly to the second terminal of the high-voltage transistor and a second terminal and a control terminal which are connected directly to a second power terminal and to the control terminal of the device, respectively. A circuit portion is provided for recovering an electrical charge discharged from the control terminal of the high-voltage transistor to the second terminal of the low-voltage transistor during the turning-off of the device.

Abstract: A radiation hardened memory device having static random access memory cells includes active gate isolation structures placed in series with oxide isolation regions between the active regions of a memory cell array. The active gate isolation structure includes a gate oxide and polycrystalline silicon gate layer electrically coupled to a supply terminal resulting in an active gate isolation structure that prevents a conductive channel extending from adjacent active regions from forming. The gate oxide of the active gate isolation structures is relatively thin compared to the conventional oxide isolation regions and thus, will be less susceptible to any adverse influence from trapped charges caused by radiation exposure.

Abstract: A sensor having high sensitivity is formed using a suspended structure with a high-density tungsten core. To manufacture it, a sacrificial layer of silicon oxide, a polycrystal silicon layer, a tungsten layer and a silicon carbide layer are deposited in succession over a single crystal silicon body. The suspended structure is defined by selectively removing the silicon carbide, tungsten and polycrystal silicon layers. Then spacers of silicon carbide are formed which cover the uncovered ends of the tungsten layer, and the sacrificial layer is then removed.

Abstract: A substitution circuit for elementary flip-flop circuits is provided to enable the automatic transposition of a flip-flop circuit whose clock signal comes from a combinational logic circuit. To do this, an over-sampled internal clock signal is used along with a synchronous pulse generator to validate the data.

Abstract: A method for performing a first programming operation on a non-volatile memory device of the type that is normally programmed by executing a pre-programming erasure algorithm and then a programming algorithm. According to the method, a non-volatile memory device is manufactured with all its memory cells in the same state, and the first programming operation for setting the memory cells to desired states is performed by executing only the programming algorithm. In a preferred method, the memory device is provided with two modes of operation: a first mode in which programming is accomplished by executing the pre-programming erasure algorithm and then the programming algorithm, and a second mode in which programming is accomplished by executing only the programming algorithm. In the preferred method, the memory device is placed in the second mode of operation before the first programming operation is performed. A non-volatile memory device having two modes of operation is also provided.

Abstract: A memory device includes a defect memory, a test circuit, and a spare memory. The defect memory and the spare memory have as many rows as the array, and each row of the defect memory and the spare memory are selected when the corresponding row of the array is selected. A test circuit locates defective cells of the array and writes addresses in the defect memory to indicate locations of the defective cells. Additionally, a control circuit selects a row of the array based on a selected row address and redirects access to the corresponding row of the spare memory whenever a selected column address corresponds to one of the addresses stored in the defect memory. In one preferred embodiment, each of the rows of the defect memory stores information indicating if there is a defective cell in the corresponding row of the array and the column address of the defective cell. A computer system including such a memory device is also provided.