Abstract: An oscillator includes four identical cells each producing a phase shift of 90 degrees. The output signal from one cell is applied to the input of the next cell, and with the cells looping back to themselves. Each cell includes a current amplifier and a parallel inductance-capacitance resonant circuit configured such that the output current from one cell is a fraction of the capacitive current of the parallel resonant circuit. This causes the 90.degree. phase shift between the input and output currents of each cell.

Abstract: A monolithically integrated signal processing circuit comprising a signal series branch connected between a signal input terminal and a signal output terminal; a reference potential terminal; a series capacitor inserted in serial manner in the signal series branch and having a parasitic capacitance acting like a capacitor that is connected between a first electrode of the series capacitor directed towards the signal input terminal and the reference voltage terminal; and a first parallel capacitor connected between the first electrode of the series capacitor and the reference potential terminal; with the first parallel capacitor being constituted at least in part by the parasitic capacitance.

Abstract: A circuit and a method generate first and second triangular waveforms opposite in phase to each other. The circuit includes a capacitor having a first plate coupled to a first output at which the first triangular waveform is produced and a second plate coupled to a second output at which the second triangular waveform is produced. First and second switches are coupled between a first voltage reference and the first and second plates, respectively, of the capacitor. The circuit also includes a controller having a first output coupled to the control terminal of the first switch and a second output coupled to a controlled terminal of a second switch. The controller is structured to produce at the first and second outputs respective first and second control signals in opposition to each other and thereby control the first and second switches in opposition to each other.

Abstract: An apparatus and method for producing a wrap-around interconnect substrate (60) comprising a substrate (42) having semi-circular vias (62) having openings (64) created by separating through cylindrical vias (62) that were positioned along cutting lines (46a, 46b) that formed part of an integrated circuit substrate strip (40) prior to separation, is disclosed.

Abstract: A non-isolated voltage converter, of switch-mode type, includes a capacitor between terminals that provide an output voltage regulated by a circuit that controls a switch that provides current to an inductive element. A local supply for the control circuit receives energy from the inductive element. In one embodiment, the inductive element has a tab between two windings, and the output voltage of the converter is smaller than the local supply voltage of the control circuit. In another embodiment, a diode is interposed between a positive terminal of the output capacitor and a positive terminal of a capacitor of the local supply of the control circuit. The negative terminal of the local supply capacitor is connected to the mid-point of a series association of the switch with the inductive element. A zener diode is interposed, in series with the local supply capacitor and the local supply diode, between the mid-point and the positive output terminal.

Abstract: A class AB CMOS output stage for an operational amplifier with a rail-to-rail output swing includes a pair of complementary control transistors connected in opposing phase to each other. Connection of the complementary control transistors is made between driving nodes of a pair of complementary output transistors driven by a differential signal. The differential signal is provided by a pair of differential signal input lines connected to an input stage of the operational amplifier. Biasing of the pair of complementary control transistors is by the differential signal.

Abstract: A row decoder includes a plurality of pre-decoding circuits which, starting from row addresses, generate pre-decoding signals and a plurality of final decoding circuits which, starting from the pre-decoding signals, drive the individual rows of the array of the memory device. Each pre-decoding circuit has a push-pull output circuit with a pull-up transistor and a pull-down transistor and four parallel paths for the signal, a first path, supplied with low voltage, which drives the pull-up transistor during reading; a second path, supplied with a positive high voltage, which drives the pull-up transistor during programming and erasing; a third path, supplied with a low voltage, which drives the pull-down transistor during reading and programming; and a fourth path, supplied with a negative high voltage, which drives the pull-down transistor during erasing. Two selection stages enable selectively one of the first and second path, and one of the third and fourth path, depending on the operative step.

Abstract: A monolithic integrated device includes a protection structure and is formed in a semiconductor material substrate having a first conductivity type, which device includes at least a first epitaxial layer formed on the substrate. The integrated device further includes a bipolar first transistor formed of a base region having a second conductivity type and including a first buried region formed in the first epitaxial layer, and having a first diffused region which extends from the first buried region to contact a top surface of the integrated device through a surface contact region with a high concentration of dopant material. The first transistor also has an emitter region with the first conductivity type, embedded in the base region, and including a second buried region formed on the first buried region and a second diffused region, with a high concentration of dopant material, which extends from the second buried region to contact the top surface of the integrated device.

Abstract: A band-gap regulator circuit produces a voltage reference having a temperature compensation for second order effects. The regulator circuit includes: a Brokaw cell for producing a first band-gap voltage reference Vbg; a circuit portion including a comparator connected to the Brokaw cell output for providing a compensation voltage value Vcorr; and a summing circuit that sums together the compensation voltage value Vcorr and the first band-gap voltage reference Vbg.

Abstract: A method of testing a processor controlled chip having embedded circuitry devoid of a direct connection external to said chip. Tracing circuitry embedded on the chip is programmed to detect the presence of specified information on a bus system embedded on the chip and devoid of a direct connection external to the chip. An address comparator detects the presence of the specified information on the bus system and opens gating circuitry in response to the detection. The specified information is extended through the gating circuitry and written in a buffer memory. The specified information can be read out of the buffer memory and extended to a user terminal external to the chip.

Abstract: A device for directly loading data onto bit lines of DRAMs. The device eliminates the need for performing a read cycle prior to a write cycle by bypassing the sense amplifiers of the DRAM. An I/O data line is connected to a bit line by a first transmission gate. A second transmission gate is electrically connected between the first transmission gate and the sense amplifier. A voltage level representing a data bit is loaded directly onto a bit line by turning off the second transmission gate to isolate the sense amplifier from the bit line and turning on the first transmission gate to connect the data line to the bit line. The voltage level on the bit line is then stored in a memory cell connected to the bit line.

Abstract: A method of controlling a flyback DC-DC converter includes using a primary control loop to monitor an auxiliary winding of a transformer for determining the amount of energy being transferred to a load. The voltage in the auxiliary winding is induced by current flowing in the secondary winding of the transformer. The primary control loop disables and enables the turning on of a power switch for driving the primary winding of the transformer, and detects the zero-crossing. The duration that the power switch is turned on is established by a secondary control loop using the output voltage for turning off the power switch for a new off phase. The flyback DC-DC converter further includes a fixed frequency oscillator having a frequency lower than the self-oscillating frequency of the converter. The power transferred from the primary circuit to the secondary circuit of the flyback transformer is controlled by introducing a delay on the turn-on instant of the power switch.

Abstract: A device for the resetting of a memory circuit in integrated circuit form includes means to recognize a particular sequence on one or more external signals applied to the integrated circuit, different from the sequences of operational functioning of the integrated circuit.

Abstract: A multi-head, disc drive, of a data storage system having a preamplifier that is split into a mother chip and set of daughter chips, each daughter chip corresponding to a head in the disc drive. The daughter chips contain very little circuitry, typically just a write driver, the front end of a read amplifier, a write fault detector, and a bias control circuit. Because the daughter chip contains little circuitry, it can be made much smaller and lighter than a conventional preamplifier, allowing the daughter chip to be placed on the suspension, close to the head. This allows the signal sent to and received from the head associated with a daughter chip to be strong enough not to be corrupted during transmission to the circuitry in the rest of the preamplifier. It also increases the bandwidth and reduces the power consumption of the preamplifier. The mother chip contains the remaining circuitry needed in the preamplifier and can be placed farther away, on a portion of the HSA that can support a larger chip.

Abstract: A power supply switching circuit employs hysteresis to ensure stable, timely, and accurate transition between a primary power source and a secondary power source of an integrated circuit. A comparison element of the circuit compares a first voltage signal derived from a primary voltage of the primary power source to a second voltage signal provided by the secondary power source in order to generate a compare output signal. A voltage divider element of the circuit, characterized as having a RC constant, is coupled to the primary power source and receives the compare signal generated by the comparison element and generates the first voltage signal. A bypass element of the circuit is coupled to the voltage divider element and is controlled by the compare signal to bypass the RC constant of the voltage divider element by immediately pulling the first voltage signal to the primary voltage when, after powering up the primary power source, the first voltage signal becomes greater than the second voltage signal.

Abstract: An electronic regulator for driving a power device connected to an output load having a first portion and a second protection portion, the first portion including a controlled switching element connected upstream of the power device and controlled by a timer adapted to be operated in a short circuit or overload situation of the device, such that the load current can flow in the power device in a pulsed state clocked by the timer.

Abstract: The method described provides for the formation of thin thermal oxide on areas of a silicon die intended for memory cells and other components of the peripheral circuits of the memory. To improve the quality of the oxide of the cells essentially in terms of resistance to degradation due to the passage of charges through it during the operation of the memory, the method provides for a step for the high-temperature nitriding of the oxide. According to a variant, the nitrided oxide formed on the areas intended for the components of the peripheral circuits is removed and then formed again by a similar thermal oxidation treatment followed by high-temperature nitriding.

Abstract: A socketed integrated circuit packaging system, including a packaged integrated circuit and a socket therefor, is disclosed. The integrated circuit package includes a device circuit board to which a thermally conductive slug is mounted; the underside of the device circuit board has a plurality of lands arranged in an array. The integrated circuit chip is mounted to the slug, through a hole in the device circuit board, and is wire-bonded to the device circuit board and thus to the lands on the underside. The socket is a molded frame, having a hole therethrough to receive the conductive slug of the integrated circuit package; the socket may also have its own thermally conductive slug disposed within the hole of the frame. The socket has spring contact members at locations matching the location of the lands on the device circuit board. The integrated circuit package may be inserted into the socket frame, held there by a metal or molded clip.

Abstract: A distance sensor has a capacitive element in turn having a first capacitor plate which is positioned facing a second capacitor plate whose distance is to be measured. In the case of fingerprinting, the second capacitor plate is defined directly by the skin surface of the finger being printed. The sensor comprises an inverting amplifier, between the input and output of which the capacitive element is connected to form a negative feedback branch. By supplying an electric charge step to the input of the inverting amplifier, a voltage step directly proportional to the distance being measured is obtained at the output.

Abstract: A method for saving and restoring data in the event of unwanted interruption of programming, the control logic unit of the memory controls writing of the data that would otherwise be lost and its address, in an appropriate backup memory location. To this end, the backup memory location is maintained erased, such as to allow immediate writing of the data and its address, in case of interruption of programming. To guarantee functioning even in the absence of an external supply, appropriate charge accumulators are provided, which can guarantee availability of a write-only cycle. As soon as a voltage drop is detected, the operations in progress are interrupted, and the backup operations for the data being programmed are activated; when the memory is switched on again, it is verified whether an interruption of the writing cycle has previously occurred, and thus the data saved can be recovered into the main memory.