Abstract: In a differential amplifier with asymmetrical outputs, the gates of the two load transistors are at the same specified potential and the voltage at the connection node between the load transistor and the amplifier transistor of one arm is stabilized by means of a compensation structure. This amplifier works at low VCC (e.g., less than 2 volts) while at the same time having high gain.

Abstract: A method is to characterize a process of ion implantation and includes a step of the measurement, by a spectroscopic ellipsometer, of the ellipsometric parameters (tan.psi., cos.delta.)of a film of organic resin present on the surface of a wafer that has received ion bombardment. The film of resin includes at least one upper layer of carbonized or damaged resin.

Abstract: A device for demodulating a binary signal having a predetermined carrier frequency and phase-modulated by encoded pulses. The device includes a phase-locked loop circuit having a phase comparator followed by a low-pass filter and a voltage-controlled oscillator, which is voltage-controlled by the output of the filter. The voltage-controlled oscillator outputs a binary signal that is synchronous with the modulated signal and at a frequency N times the carrier frequency. The phase-locked loop circuit also includes a divider that divides by N the output signal of the oscillator and supplies the divided signal to one input of the phase comparator. Thus, a binary signal synchronous with the modulated signal and having a frequency equal to the carrier frequency is supplied to one input of the phase comparator. The other input of the phase comparator receives the modulated signal.

Abstract: An Exclusive-OR logic gate with four two-by-two complementary inputs and two complementary outputs. The structure of this Exclusive-Or gate is said to be symmetrical in that the gate has a propagation time that is identical whichever of the two pairs of complementary inputs is switched over, whatever the nature of the transition at output and whatever the logic state of the pair of inputs that do not switch over. The disclosed device enables a further reduction in the differences in the time taken for the propagation of the signal edges through the gate by eliminating the floating character of certain nodes. It also relates to a frequency multiplier comprising a tree of Exclusive-Or gates such as this.

Abstract: This invention relates to the color matching function used in connection with the luminance or white stretch function in a television video processor. Automatic adjustment in the amplitude of the color difference signals is provided to compensate for the effect of the stretch of the luminance signal in a provision called color matching. The general principal of color matching being, any percentage change in the amplitude of the luminance signal due to the white stretch effect, must be balanced by the same percentage changes in the color difference signal so that the ratio of the color signals can be maintained after matrixing. This accomplished by compensating the color difference signals by a varying amount that decreases with increasing the input luminance signal level when the level of the input luminance signal is above said selected threshold.

Abstract: A circuit for providing a D.C. voltage of high value from the output of a rectifying bridge on a capacitor of high capacitance, and for providing low supply voltages, including a first diode connected between the output of the rectifying bridge and the capacitor, first and second cascode-mounted transistors, circuitry for setting the potential of the control terminal of the first transistor, circuitry for reducing the potential of this control terminal when the rectified voltage exceeds a predetermined value, a regulation circuit connected at the connection node of the first and second transistors, and circuitry for applying, to the second transistor, a turn-on pulse of determined duration after the output voltage of the bridge has exceeded the determined value.

Abstract: A method is for driving a multiphase brushless motor with N windings connected in a star or in a polygonal configuration. The windings are driven according to a certain periodic voltage profile. The method includes cyclically keeping for a certain time interval at least one of the N windings in a fixed state of low or high saturation and applying to the other phase windings instantaneous voltages according to a predefined different periodic voltage profile such that the resultant voltages on the windings are coherent with the certain periodic voltage profile. The number of intervals, in an entire electrical period, in which the fixed high or low saturation state of one winding is produced, depends on the predefined driving profile and upon the number N of windings of the motor.

Abstract: A process for fabricating a metal-metal capacitor within an integrated circuit comprises the steps of: producing a first metal electrode, a second metal electrode, and a dielectric layer on top of a lower insulating layer; and depositing an upper insulating layer on top of the two metal electrodes and the dielectric layer. The integrated circuit comprises the lower insulating layer, a first metal layer which is on top of the lower insulating layer, and the upper insulating layer which is on top of the first metal layer. The capacitor comprises the first metal electrode, the second metal electrode, and the dielectric layer wherein each of the two metal electrodes is in contact with one side of the dielectric layer. The electrodes and the dielectric layer lie between the lower insulating layer, which supports a level of metallization (M1), and the upper insulating layer which covers this level of metallization.

Abstract: An integrated amplifier includes a differential input stage including a first pair of bipolar junction transistors. A reference bias current generator biases the differential input stage with a reference bias current. A first and a second current mirror circuit drives a respective transistor of the first pair of bipolar junction transistors. Each of the first and second current mirror circuits includes a transistor having a base terminal connected to an intermediate node. An integrated resistor is connected to the intermediate node and is in series with the respective transistor of the first pair of bipolar junction transistors. The reference bias current of the differential input stage conducts through the integrated resistor. The reference bias current corresponds to a ratio between a base emitter junction voltage and a resistance of the integrated resistor.

Abstract: A shielded electrical connection of the integrated type comprises a connection element and a shielding element. The connection element includes a first substantially planar structure of a first conducting material and is placed vertically above and isolated from a semiconductor substrate and which occupies a first flat region. The shielding element includes a second substantially planar structure of a second conducting material and is placed vertically between the first structure and the substrate and which occupies a second flat region. A third substantially planar structure made of a third conducting material is placed vertically above the first structure and which occupies a third flat region. The first region does not extend outside the second and third regions. Furthermore, the second and third structures are connected electrically together and to a reference of potential and are electrically insulated from the first structure and the substrate.

Abstract: A device generates pulses of high-precision with programmable duration. The device includes first, second and third pulse generator circuits. The first pulse generator circuit receives at an input a pulse generation command signal, and provides at an output a first pulse for loading the contents of a register in a counter. The second pulse generator circuit is triggered by the first pulse provided by the first pulse generator circuit. The third pulse generator circuit is triggered by a second pulse provided by the second pulse generator circuit, and generates a third pulse to restart the second pulse generator circuit. The second pulse provided by the second pulse generator circuit forms a clock signal for the counter to produce a decrement in the counter. The output signal from the counter is the pulsed signal to be generated. The duration of the pulsed signal is determined by the content of the counter.

Abstract: An electromagnetic head for a storage device comprises a magnetic core forming a magnetic circuit, and a magnetoresistive means. The magnetic core is interrupted by an air-gap, thereby separating a first pole and second pole of the magnetic core. The magnetoresistive means is disposed in the region of the air-gap, and is connected to the magnetic core so as to be connected in the magnetic circuit.

Abstract: A current bias, current sense magneto-resistive preamplifier for a hard disk drive and related methods preferably includes an MR sensor responsive to a current bias for sensing a change in magnetic data flux and responsively providing a change in electrical resistance. A preamplifying circuit is preferably connected to the MR sensor for providing the current bias thereto and for amplifying a detected change in electrical resistance. The preamplifying circuit includes a sensor biasing circuit for providing the current bias to the MR sensor and an amplifying output circuit for providing an amplified output signal representative of the detected change in current bias to the MR sensor. The sensor biasing circuit preferably includes a current source, a first amplifying circuit connected to the MR sensor for sensing the change in electrical resistance therefrom, and a second amplifying circuit having a first input connected to the first amplifying circuit and a second input connected to the current source.

Abstract: A first current generator which generates a current that is based on the threshold difference of enhancement-type and native-type transistors therein. A second current generator which generates a current that is based on the thermal voltage. The currents generated by the first and second current generators are linearly combined to produce a highly temperature-stable current.

Abstract: A DMOS device in a complex integrated circuit having a well region defined by a buried isolation region and an overlapping deep drain region within an epitaxial layer formed over a substrate, a body region having two source regions within the well region, insulated gates over the two source regions, and a Schottky contact over a central portion of the well region and spaced from the body region. The Schottky contact defines a Schottky diode within the epitaxial layer for diverting current from the substrate in the event of a below ground effect or an oversupply effect. The invention reduces or eliminates altogether the effects of parasitic transistors in the complex integrated circuit.

Abstract: A parallel pipelined analog-to-digital converter for use with chips containing large arrays of detectors is described. In these A/D converters, the degree of parallelism decreases between earlier and later pipeline stages. That is, there are fewer instances of at least one of the later stages than there are instances of at least one of the earlier stages. Thus, the instances of the earlier stages are responsible for processing a fewer number of pixels than are instances of the later stages. Viewed another way, the parallel pipelined analog-to-digital converter architecture of this invention assumes a tree or branched arrangement in which the earlier stages correspond to leaves and the later stage condense to branches. In an extreme example, the later stages coalesce to a single route.

Abstract: A programmable dividing circuit comprises a first plurality N of similar transistor stages connected in a divide-by-N sequence, wherein N is an odd integer, the transistor stages being configured so that when an output of the last stage is supplied to a first stage in the sequence, the dividing circuit operates as a divide-by-N circuit in which an output signal is generated which has one cycle for every N cycles of a clock signal applied to the transistor stages.

Abstract: The selector circuit is particularly well suited to the switching over of two voltages VPP1 and VPP2, greater than the supply voltage Vcc of an integrated circuit without a priori knowledge of which of the two voltages is the highest. The selector circuit includes first and second switch circuits coupled by first and second MOS transistors whose well is biased by the output voltage of the selector circuit.

Abstract: An AC and DC input power supply includes an AC power supply circuit and an AC input for receiving a range of AC input voltages. A rectifier circuit is connected to the AC input. An isolation output transformer has first and second primary winding terminals and a low voltage winding section for connecting to a DC voltage input that is lower than the range of the DC voltage that is rectified from the range of AC input voltages. The rectifier circuit is connected to the first primary winding terminal of the isolation output transformer. A transistor is connected to the second primary winding terminal of the isolation output transformer. The DC power supply circuit includes a DC input that is selectably connectable between the first primary winding terminal when the voltage input to the DC input connector is a nominal DC voltage that is within the range of the DC bulk voltage and the low voltage winding section when the voltage input to the DC input is lower than the range of the DC bulk voltage.

Abstract: A switched capacitor wherein one of the plates of the capacitor to be switched is fed with the input signal via a transistor switch receiving as control signal at the gate thereof a pulse train with predetermined frequency. For compensating the parasitic capacitance of the transistor switch, a compensation component is located between the transistor switch and the capacitor to be switched. This compensation component is formed as an incomplete transistor structure, such as only 1/2 of a transistor, has a drain region in common with transistor switch and has an insulated gate. The parasitic capacitance of the compensation component thus is established mainly by the capacitance between the insulated gate and the drain region and thus corresponds to the parasitic capacitance of the transistor switch, whereby complete compensation with optimized charge transfer is achieved.