Abstract: A device for analog programming is disclosed. The device comprises a current mirror circuit connected to drain terminals of a cell to be programmed and of a MOS reference transistor. An operational amplifier has inputs connected to the drain terminals of the cell and respectively of the MOS transistor and an output connected to the control terminal of the MOS transistor. During programming, the control and drain terminals of the cell are biased at corresponding programming voltages and the output voltage of the operational amplifier, which is correlated to the current threshold voltage level of the cell, is monitored and the programming is interrupted when this output voltage becomes at least equal to a reference voltage correlated to the threshold value desired for the cell.

Abstract: A control circuit comprises a plurality of input terminals and an output terminal for biasing a floating well in a semiconductor integrated circuit structure. The control circuit also includes a first transistor which has its conduction terminals connected between a first input terminal and an output terminal, and a second transistor which has its conduction terminals connected between a second input terminal and the output terminal. The control circuit further includes a regulator coupling the output terminal to each of the control terminals of said first and second transistors.

Abstract: An integrated electronic control circuit comprises a microcontroller connected to at least one volatile memory, at least one input/output port, a plurality of control devices, and an electronic non-volatile memory device comprising a non-volatile memory cell matrix linked to a control register, and a switch element connected between a voltage reference and the cell matrix to enable the program mode of the cell matrix under control by the microcontroller.

Abstract: A low/zero power memory device includes a deselect mode of operation wherein row decoders, column decoders, write decoders, pre-coders, post-coders and like operational circuits of the memory device needed for wordline and column activation are disabled until such time as a memory device supply voltage exceeds a certain threshold. An included test mode circuit detects test mode activation and overrides application of the power fail deselect mode of operation of the device. This activates the wordline and column related operational circuits immediately at power up such that the device powers up with multiple wordlines and columns activated and ready for application of a stress test overvoltage.

Abstract: A semiconductor device having separated exchange mechanism comprises a chip forming an integrated circuit; a connection substrate; device connection points or balls; and at least one exchange mechanism. The connection substrate comprises an external connection mechanism. The device connection points or balls are distributed in the form of a matrix and are located between the juxtaposed faces of the chip and of the connection substrate. The device connection points are connected to the external connection mechanism. The exchange mechanism comprises two parts. The two parts are arranged so as to be separated from each other and capable of exchanging signals between each other, in one or both directions. The first part is physically coupled to the chip. The second part is physically coupled to the connection substrate and is connected to the external connection mechanism.

Abstract: The invention relates to a circuit architecture for easily carrying out tests on a non-volatile memory device having at least one matrix (2) of memory cells. The architecture is distinctive in that it comprises a bi-directional internal data bus (3) extending from one end to the other of the memory device, a plurality of signal sources (8) inside said memory device, at least one local bus (6) connected to the data bus (3), and timing means (10) for timing the access of the local bus (6) to the data bus (3) and the selective access of the signal sources (8) to the local bus (6) during the same test cycle.

Abstract: A circuit and method for measuring a back EMF voltage of a voice coil in a mass storage device, or the like, includes an amplifier connected across the coil to produce an output signal proportional to a voltage across the coil and a circuit connected to selectively connect the output signal of the amplifier to a circuit output when a driving current is not applied to said coil. A sample window is generated after drive currents within the coil have been allowed to decay to zero, and between a time during which a PWM signal changes from negative to positive and a time when the PWM waveform crosses a voltage error value.

Abstract: An electrical connection device for electrically connecting an electronic component of the type having electrical connection points. The electrical connection device includes electrical connection members that each have a tip that can retract against an elastic means, a support carrying the electrical connection members, and a movable receptacle. The movable receptacle can house an electronic component and can bring the electronic component into a connection position in which the tips of the electrical connection members bear on the electrical connection points of the electronic component. In a preferred embodiment, the electrical connection members are removable from the device. Additionally, a testing apparatus that includes such an electrical connection device is provided.

Abstract: A flyback DC--DC converter employs a flyback transformer for storing and transferring energy to a load having an auxiliary winding whose voltage is compared by a comparator with a threshold to detect its crossing. As a consequence, a power transistor driving the primary winding of the transformer is switched on through a control flip-flop, for a new phase of conduction and accumulation of energy, whose duration is established by a secondary control loop of the output voltage producing the switching off of the power transistor for a successive energy transfer phase toward the load of the energy stored in the transformer during the preceding conduction phase. The converter has a wholly integrated control circuit that includes a second comparator of the voltage existing on the current terminal of the power transistor connected to the primary winding of the transformer with respect to the ground potential of the circuit.

Abstract: The method is for the control of an electrical oven and includes taking into account the temperature and/or the humidity level of the air measured by sensors in the interior of a cavity of an oven in which food to be heated and/or cooked is placed. The instantaneous value of the supplied power of the magnetron of the oven and the duration of a heating cycle are controlled, such as by fuzzy logic.

Abstract: Method and system for monitoring a plasma etch process performed in a plasma processing chamber, the method and system being capable of accurately monitoring and controlling the plasma etch process without being affected by the change in a plasma light emission transmission characteristically caused by process polymer depositions on a detecting surface or sampling window.

Abstract: The device is to be used with a parallel architecture partial response maximum likelihood (PRML) reading apparatus comprising a variable-gain input amplifier, a low-pass analog filter, a transversal continuous-time analog filter and two distinct and parallel processing channels interposed between the transversal analog filter and an RLL-NRZ decoder. The two processing channels comprise respective analog-digital converters and respective Viterbi detectors and operate according to sampling sequences that alternate with one another. The device for processing the servo signals comprises a rectifier connected to the outputs of the analog-digital converters and an integrator.

Abstract: The method comprises the steps of detecting the trailing edge of an initialization signal, and generating a read bias signal and a read activation signal for the cell, when the trailing edge of the initialization signal is detected. The signals of read bias and read activation have a ramp-like leading edge and both signals are disabled when reading of the cell is completed. Thereby, phenomena of soft-writing of the cell are avoided, and risks of erroneous readings are reduced.

Abstract: A method and a circuit generate a pulse synchronization signal (ATD) for timing the memory cell read phase in semiconductor integrated electronic memory devices. The pulse signal (ATD) is generated upon detection of a change in logic state of at least one of a plurality of address input terminals of the memory cells. The method consists of duplicating the ATD signal into at least one pair of signals and propagating such signals through separate parallel timing chains at the ends of which the ATD signal is reinstated, the chains being alternately active.

Abstract: A circuit for charging a capacitance using an LDMOS integrated transistor functioning as a source follower and controlled, in a manner to emulate a high voltage charging diode of the capacitance. The LDMOS transistor is controlled via a bootstrap capacitor charged by a diode at the supply voltage of the circuit, and by an inverter driven by a logic control circuit as a function of a Low Gate Drive Signal and of a second logic signal which is active during a phase wherein the supply voltage is lower than the minimum switch-on voltage of the integrated circuit. The circuit uses a first zener diode to charge the bootstrap capacitor and the source of the transistor is connected to the supply node through a second zener diode.

Abstract: A current mirror circuit is provided with recovery having high output impedance. The current mirror includes a differential stage having a pair of transistors, and a voltage feedback loop which is stabilized and closed on a first one of the transistors of the differential stage. A second one of the transistors of the differential stage is connected, by its base terminal, to the collector terminal of an output transistor and, by its collector terminal, to the supply voltage. Moreover, the circuit includes a positive feedback loop which has the second transistor of the differential stage and the output transistor. A low-impedance circuit branch is connected to the base terminal of the second transistor of the differential stage and to the collector terminal of the output transistor.

Abstract: An integrated circuit and associated method for switching from a power supply to a battery are provided. The integrated circuit preferably includes a memory circuit responsive to an external power supply and to a battery for storing data therein and a sleep mode latching circuit connected to the memory circuit for latching the memory circuit in a reduced power sleep mode condition so as to reduce power usage of a battery and a non-sleep mode operating condition so as to allow normal operation of the memory circuit by a power supply. The integrated circuit preferably also includes a sleep mode latch locking circuit connected to the sleep mode latching circuit and the memory circuit and responsive to a power supply for locking the sleep mode latching circuit in the non-sleep mode operating condition when power supplied from the power supply falls below a predetermined threshold so that the memory circuit is inhibited from inadvertently entering the reduced power sleep mode condition.

Abstract: The present invention relates to a buffer for logic signals including a MOS output transistor of a first conductivity type connected by its source to a first supply potential, the drain of this transistor forming an output terminal of the buffer; a control transistor for controlling the output transistor connected between the gate of the output transistor and a second supply potential; a third transistor of the first conductivity type connected between the gate of the output transistor and the first supply potential and controlled to maintain the gate-source voltage of the buffer close to a threshold voltage so that the output transistor operates as a current generator; and a fourth transistor connected to render floating the gate of the third transistor when the potential on the output terminal is close to the first supply potential.

Abstract: A memory, such as a static random access memory (SRAM), includes at least one memory cell. The bit lines for that memory cell are selectively connected to corresponding write bit lines through a column select pass transistor and a selectively blowable fuse. A reset circuit is connected to the same write bit lines through a fuse structure mimic circuit. Responsive to data transitions on the write bit lines, the reset circuit operates to detect the occurrence of a memory operation to the memory cell and generate a reset signal for resetting the memory in preparation for a next write operation. To support substantially simultaneous presentation of write data to both the reset circuit and the memory cell, the fuse structure mimic circuit delays presentation of the write bit line data to the reset circuit.

Abstract: The invention comprises a magnetic disk storage system and comprises method for configuring the magnetic disk storage system. The magnetic disk storage system facilitates write and read operations that compensate for variances that are experienced with magnetic disk storage systems. When writing data to a data sector, the magnetic disk storage system utilizes a phase lock oscillator field that has a length that is specified for that data sector. When reading from a data sector, the magnetic disk storage system utilizes an incremental read delay that has a duration that is specified for that data sector. Data sectors with shorter data sector delay periods can have shorter phase lock oscillator fields than data sectors with larger data sector delay periods. This frees-up memory space and increases the capacity and performance of the magnetic disk storage system.