Abstract: A device for generating a voltage pulse in a low-voltage integrated circuit includes a capacitor and a control circuit. An input signal having negative pulses is received by the device. The input signal has a high level corresponding to a level of a logic supply voltage for the device, and a low level corresponding to zero volts. The control circuit includes a first and a second circuit element. The first circuit element transmits the low level of the input signal to a second terminal of the capacitor and also provides the capacitor a charging path. The second circuit element transmits the low level of the input signal to a first terminal of the capacitor with a predetermined delay so that a negative pulse between the high level and a negative level is provided at the second terminal of the capacitor in response to the input signal.

Abstract: A cathode-ray tube video device connected to a power source and having a first normal operating state and at least a second operating state at reduced power (stand-by mode) includes a switching power supply and a circuit portion for demagnetizing the cathode-ray tube coupled to the power source through an electrically actuated switch. The switch is closed to demagnetize the cathode-ray tube during the first operating state of the device, and opened during the second operating state at reduced power of the device.

Abstract: A structure and method for creating an integrated circuit passivation (24) comprising, a circuit (16), a dielectric (18), and metal plates (20) over which an insulating layer (26) is disposed that electrically and hermetically isolates the circuit (16), and a discharge layer (32) that is deposited to form a passivation (24) that protects the circuit (16) from electrostatic discharges caused by, e.g., a finger, is disclosed.

Abstract: A current-controlled oscillator includes a capacitor, and at least one current source for providing at least one charge current for charging the capacitor. A discharge circuit sequentially discharges the capacitor with a discharge current. A control circuit maintains a mean charge voltage of the capacitor at a preset value by controlling the discharge current. The control circuit includes a current control source forming a current mirror with the at least one current source. The current control source is connected to the discharge circuit for setting the discharge current substantially equal to a sum of the charge currents. The oscillator further includes a correction circuit for correcting the discharge current corresponding to a mean charge of the capacitor.

Abstract: A DC/DC conversion circuit, adapted to convert a DC input voltage to a DC output voltage, employs a PNP type of bipolar power transistor as a synchronous rectifier element, to allow power-on through a simplified control circuitry capable of sensing, automatically and at a high speed, the difference of potential across the switch. This approach allows power to be transferred from the input to the output unilaterally, while automatically controlling the depth of saturation of the power transistor and regulating its base current.

Abstract: A structure and method for creating an integrated circuit passivation comprising, a circuit (16) over which an insulating layer (26 and/or 28) is disposed that electrically and hermetically isolates the circuit (16) and a silicon carbide layer (30) to form a passivation (24) to protect a circuit (16), is disclosed.

Abstract: A method for starting a polyphase DC motor having a rotor. The position of the rotor is detected by initiating current in each of the phases of the motor and measuring a time period between the initiation of current in the coil and an instant when the current exceeds a threshold current. The phase in which the current reaches the threshold in the shortest amount of time is the phase closest to the position of the rotor. A phase closest to the position of the rotor is identified in each of an odd number of trials, and a starting phase is selected as the phase identified in the majority of trials. The motor is started by providing current to the starting phase.

Abstract: The controlled erase method includes supplying at least one erase pulse to cells of a memory array; comparing the threshold voltage of the erased cells with a low threshold value; selectively soft-programming the erased cells which have a threshold voltage lower than the low threshold value; and verifying whether the erased cells have a threshold voltage lower than a high threshold value, which is higher than the low threshold value. If at least one predetermined number of erased cells has a threshold voltage which is higher than the high threshold value, an erase pulse is applied to all the cells and the steps of comparing, selectively soft-programming and verifying are repeated.

Abstract: A temperature compensated clock and method of clocking systems are provided. The clock preferably has an oscillator for generating an oscillating waveform signal at a preselected frequency and a frequency divider responsive to the oscillator for dividing the frequency of the oscillating waveform signal. A temperature monitoring circuit is positioned responsive to a voltage input signal independent of temperature and a voltage input signal proportional to temperature for monitoring temperature variations. A temperature compensating circuit, preferably including a programmable scaling circuit, is responsive to the frequency divider and the temperature monitoring circuit for scaling the divided frequency of the generated waveform and thereby advantageously produces a temperature compensated output timing signal.

Abstract: The invention relates to a method of automatically shifting from the fabrication of an EPROM cell to the fabrication of a ROM cell, which method is specifically intended for semiconductor electronic circuits having a resident memory and is of the type wherein the structure of at least one memory cell transistor is defined on a semiconductor substrate using photolithographic techniques including an active area and a channel region, the cell being adapted to acquire a logic state selected by the user. Advantageously, the conductivity of the active area is changed to suit the logical contents that the cell is intended to contain.

Abstract: A process for manufacturing semiconductor packages comprising, respectively, a substrate, a chip which forms an integrated circuit and is attached to one region of the substrate, electrical connection means connecting the chip to a group of external electrical connection regions lying on one face of the substrate, as well as an encapsulation encasement. The process consists in producing, in a matrix configuration, a multiplicity of groups of connection regions (104a) on a common substrate plate (102), corresponding to as many chip attachment regions (109), in attaching a chip (103) to each attachment region (109) of the common substrate plate, in electrically connecting each chip (103) to the associated electrical connection regions (104a), so as to obtain an assembly (111) consisting of the substrate plate and the connected chips.

Abstract: Composite layers of titanium silicide and polysilicon define a fuse resistor within a programmable fuse element that increases its resistance from about 50 ohms in the unprogrammed state to about 250 K-ohms in the programmed state by creating a discontinuity in the silicide layer immediately over a PN junction in the polysilicon layer. The resistance of the fuse resistor in the programmed state is determined by the reverse-biased diode characteristic of the PN junction. Portions of a metallic layer overlie portions of the fuse resistor except at the site of the PN junction in the polysilicon layer so that the silicide is preferentially heated immediately above the PN junction to cause the discontinuity to occur at that site. The metallic layer portions serve both as a heat sink for the underlying portions of the silicide layer and as electrical connections to the fuse resistor.

Abstract: A method of forming an isolation region in an integrated circuit and an integrated circuit formed thereby. A method preferably includes forming at least one trench in a semiconductor substrate, forming an insulation layer of material in the at least one trench and on peripheral regions of the at least one trench of the semiconductor substrate, forming a sacrificial layer of material on the insulation layer having a different polishing rate than the insulation layer, and polishing the layer having the different polishing rate and portions of the insulation layer so that the sacrificial layer having the different polishing rate and portions of the insulation layer are removed, so that other portions of the insulation layer remain in the at least one trench of the substrate, and so that the upper surface of the at least one trench and the peripheral regions thereof in combination provide a substantially planar surface.

Abstract: The invention is a servo compensation method and system for use in a disk storage system. The disk storage system experiences error that causes a head to become mis-aligned with the disk. The error comprises run-out error and other servo position errors. During follow mode, a digital filter processes a position error signal to generate a compensation signal. The position error signal is comprised of components representative of the run-out error and the other servo position errors. The compensation signal is comprised of components that cause the servo positioning system to compensate for the run-out error and the other servo position errors. The digital filter also operates as an oscillator that provides an oscillating signal the spin frequency of the disk during seek mode.

Abstract: A power MOSFET suitable for use in RF applications and a method for making the same is disclosed. The power MOSFET reduces the gate coverage of the drain region of the device in order to decrease the device gate to drain capacitance C.sub.gd. A significant portion of the gate overlaying the drain region is eliminated by the removal of a portion of a polysilicon layer that is disposed over a substantial portion of the drain region that resides between the channel portions of the body regions of the device. The resulting open area, that is subsequently covered by an oxide layer, separates the polysilicon gate electrodes of the device. Finally, a metal layer is deposited over the entire structure to form the gate and source electrodes of the device.

Abstract: A method and a circuit for controlling a slew rate of a coil in a voice coil motor in a disk drive system. A slew rate control signal is generated by a microprocessor or by an analog circuit in response to one or more operating parameters of the disk drive system. A driver circuit selectively couples the coil between a voltage source and a ground in response to a driver signal, and controls the slew rate of the coil in response to the slew rate control signal.

Abstract: A multiple-level memory cell is capable of taking on a plurality of states, with each state being represented by a different value of a physical quantity and being associated with a corresponding logic value. A method for reading the memory cell includes the step of setting an actual physical quantity to a value correlated with the value of the physical quantity corresponding to the state of the memory cell. This step is repeated until the logic value corresponding to the state of the memory cell is determined. A cycle includes the step of setting a component of the logic value to a value which is a function of a range in which the actual physical quantity lies, as determined by comparing the actual physical quantity with at least one reference physical quantity having a predetermined value lying between a minimum value and a maximum value for the actual physical quantity.

Abstract: A power supply switching circuit ensures stable, timely, and accurate transition between a primary power source and a secondary power source of an integrated circuit. A comparison element of the circuit compares a first voltage signal derived from a primary voltage of the primary power source to a second voltage signal, also derived from the primary voltage but having a different rate of change than the first voltage signal, to generate a compare output signal. The first and second voltage signals are characterized as being equal to each other when the primary voltage is equal to a predetermined crossover point at which the integrated circuit device will be powered by the primary voltage.

Abstract: A semiconductor integrated circuit comprises a substrate including a plurality of transistors, and a conductive line for coupling at least two of the transistors with each other, each transistor comprising a drain diffusion region, a source diffusion region, a gate region, and a test diffusion region within the substrate, the test diffusion region being electrically coupled to a metal line within the semiconductor integrated circuit for establishing an indication of the voltage at the probing diffusion region.

Abstract: A circuit and method for clocking counters in a polyphase dc motor is provided in which the motor is capable of operating at two or more operating states, spin-up and regulation. The system clock is connected to the clocking circuit through dividers to produce a first clock signal having a low frequency for operating the counter at spin-up, and a second clock signal having a higher frequency for operating the counter at regulation. The clocking circuit includes a switch for connecting the first clock signal to the clock input of the counter when the motor is at spin-up, and for connecting the second clock signal to the clock input when the motor is at regulation. The switch is controlled by a switch control circuit that ensures that switching does not occur when the counter is timing the motor by only allowing the switching to occur when the counter is at an end of a timing cycle and before the counter resets. An at-speed circuit is used to determine whether the motor is at spin-up or at regulation.