Abstract: A switching circuit comprising a supply voltage, a reference voltage, a line suitable to carry a negative voltage, an input for a control signal, suitable to supply to a first output node and to a second output node two voltages respectively equal to supply voltage and to line voltage or, alternatively, to line voltage and to supply voltage, in response to the control signal.

Abstract: Disclosed is a compact disc apparatus having automatic start capabilities. The compact disc apparatus includes a digital signal processor for reading sectors that have a plurality of EFM frames, and the EFM frames contain at least a data component and a subcode component. Also included is a Q-subcode extractor for retrieving a Q-bit from each of the plurality of EFM frames being read by the digital signal processor. An auto-start unit is further included to analyze and process the retrieved Q-bits from each of the plurality of EFM frames, such that a determination is made as to whether a minute/second/frame derived from the retrieved Q-bits matches a desired start minute/second/frame location. Wherein the data being read from sectors by the digital signal processor starts transferring data to a memory beginning with the desired start minute/second/frame when the match is found by the auto-start unit.

Abstract: A motor control circuit control the operation of a motor that includes a motor coil. The motor control circuit includes an analog driver structured to supply the motor coil with a supply voltage in response to receiving an analog driver input signal. Coupled to the analog driver is a digital-to-analog converter that is structured to convert a digital motor control signal to the analog driver input signal. Coupled to the digital-to-analog converter is a lever shifter that is structured to receive a low voltage digital command signal from a digital motor controller. The level shifter is also structured to increase the voltage of the digital command signal to produce the digital motor control signal and provide the digital motor control signal to the digital-to-analog converter.

Abstract: A method of parking the head by first moving the head toward the inner diameter of the disc an then back across the disc and parking the head on a flat part of a ramp. In one embodiment, a moderate voltage on the motor drives the head toward the inner diameter of the disc until the head hits the inner crash stop and then a moderate current drives the head back across the disc to give the head enough momentum to get to the flat part of he ramp. In another embodiment, more stages, each having a different voltage, are used to get better control of the velocity of the head as it is being driven across the disc. A higher voltage is also used to turn the head to move toward the inner diameter of the disc when it is moving fast toward the outer diameter. A retract circuit controls the movement of the head during retract. To be able to drive the head in the tow directions, the retract circuit needs to be bipolar, containing both a current source and a current sink. Counters are used to time the driving of the head.

Abstract: An integrated circuit structure and method provides for an integrated circuit device to respond to an edge transition detection (ETD) pulse in one of two ways. First, in response to the ETD pulse, the integrated circuit device exits a test mode at least temporarily every cycle of the integrated circuit device. Second, a node of the integrated circuit device is re-initialized every cycle if it is not forced by a super voltage indicative of test mode entry. Both of these responses prevent accidental entry of the integrated circuit device into the test mode. If the integrated circuit device is supposed to be in the test mode, it stays in the test mode. If, however, the integrated circuit device is not intended to be in the test mode, the ETD pulse forces the integrated circuit device out of the test mode. Subsequent entry into the test mode of the device is permitted if conditions for entry into the test mode have otherwise been met.

Abstract: A circuit for charging a capacitance using an LDMOS integrated transistor functioning as a source follower stage and controlled, in a manner to emulate a high voltage charging diode of the capacitance via a bootstrap capacitor charged by a diode connected to the supply node of the circuit, and by an inverter driven by a logic control circuit as a function of a first Low Gate Drive Signal and of a second logic signal. The second logic signal is active during a phase where the supply voltage is lower than the minimum switch-on voltage of the integrated circuit. The circuit further includes a second inverter functionally referred to the charging node of the bootstrap capacitor and to the voltage of the output node of the inverter. The second inverter has an input coupled to the second logic signal and an output coupled to the gate node of the LDMOS transistor for preventing accidental undue switch-on of the LDMOS transistor.

Abstract: An integrated circuit and method are provided for sensing activity such as acceleration in a predetermined direction of movement. The integrated released beam sensor preferably includes a switch detecting circuit region and a sensor switching region connected to and positioned adjacent the switch detecting circuit region. The sensor switching region preferably includes a plurality of floating contacts positioned adjacent and lengthwise extending outwardly from said switch detecting circuit region for defining a plurality of released beams so that each of said plurality of released beams displaces in a predetermined direction responsive to acceleration. The plurality of released beams preferably includes at least two released beams lengthwise extending outwardly from the switch detecting circuit region to different predetermined lengths and at least two released beams lengthwise extending outwardly from the switch detecting circuit region to substantially the same predetermined lengths.

Abstract: An electronic device smoothes a charge current peak in RLC output stages of switching step-up regulators, which stages include an input terminal and an output terminal with an inductance and a parasitic resistance in series therebetween, the latter corresponding to the series parasitic resistance of the inductance, and a capacitor connected between the output terminal and a ground. The device comprises a parallel of a resistor and a controlled switch connected between the inductance and the output terminal of the stage upstream of the capacitor. Advantageously, the switch would only be open during the charge transient of the capacitor.

Abstract: A relaxation oscillator includes a first capacitor at the terminals of which there is a first voltage V.sub.1, a circuit to charge the first capacitor from a power supply voltage, a circuit to discharge the first capacitor, and a switch which alternately charges and discharges the first capacitor responsive to a control signal. The relaxation oscillator also includes a relaxation circuit to generate the oscillation signal and the control signal from the first voltage. The oscillator also includes a regulation circuit to cause the first voltage applied to the relaxation circuit to be approximately equal to a reference voltage. The circuit for charging the first capacitor includes a resistance R.sub.1. The relaxation oscillator is particularly applicable to phase locked loops.

Abstract: A method and device of protection from the effects of a persistent short circuit of the output of a DC-DC flyback converter self-oscillating either at a variable frequency or functioning at a fixed frequency in a discontinuous manner is provided. The voltage induced from the current flowing in a secondary winding of a transformer on the auxiliary winding is rectified and filtered to power, during a steady state of operation, the control circuitry of the converter. The turning on of the power switch is driven during a start-up or recovery phase by a primary control loop, when the supply voltage of the control circuit reaches or is over a preestablished enabling threshold of the control circuit. A secondary control loop includes a photocoupler of the output error voltage to an input of the control circuitry to which a compensation capacitor is connected.

Abstract: Monitoring of current flowing through an inductive load driven through a bridge power stage in a PWM mode, comprises sampling the signal output by a sensing amplifier with a Sample & Hold circuit including a sampling switch and a storing capacitor. The average value of the current in the load is monitored by sampling at a half way point of an active driving phase and at a half way point of a current recirculation phase by closing the switch with a synchronizing pulse that coincides with the half way points of these phases of operation. The monitoring uses a pair of complementary periodic reference signals and uses a sensing amplifier to amplify the signal existing on a current sensing resistor functionally connected in series with the load. This produces an amplified signal representative of the current in the load to be fed to an input of an error amplifier driving a power amplifier of the bridge stage.

Abstract: A glitch immune ATD circuit for electronic memory devices includes a plurality of input pads (A<0>, . . . , A<N>) of the memory device each one connected to a corresponding address input buffer (I0, . . . , IN), with each input buffer comprising an output terminal connected to a corresponding input of a local ATD generator circuit (ATD.sub.-- GEN.sub.-- LOC). The circuit also has an output for each local generator (ATD.sub.-- GEN.sub.-- LOC) connected to a corresponding input of a logic gate having a plurality (N) of inputs and an output (Y). A global ATD generator circuit has one input connected to the output (Y) of the logic gate and producing a final ATD pulse. The global ATD generator circuit includes a master slave device which is controlled by an input signal (NOTCLK) received from the output (Y) of the logic gate; a central and final ATD generator (ATD.sub.-- GEN.sub.

Abstract: An integrated structure comprises a protective Zener diode connected between a first and a second terminal of the structure, and is formed in a chip of semiconductor material within an insulating region. The structure includes first and second biasing Zener diodes connected back-to-back between the first and the second terminals of the structure. The first and the second biasing diodes are disposed respectively in the opposite direction to and in the same direction as the protective diode, and having a common terminal connected to the insulating region. The protective diode has a reverse threshold voltage lower than a reverse threshold voltage of the second biasing diode.

Abstract: The control of the current in a PWM mode through independently controlled windings of a multi-phase motor driven in a "bipolar" mode is implemented by employing only two sense resistors and related control loops. This is so regardless of the actual number of windings of the motor.

Abstract: A disc drive apparatus and a method for synchronizing information components read from a compact disc media are described. The method includes selecting a start minutes/seconds/frames MSF for a data component and triggering a transfer of the data component to a buffer when the start minutes/seconds/frames for the data is detected. The method also includes selecting a start minutes/seconds/frames for a subcode component and triggering a transfer of the subcode component to the buffer when the start minutes/seconds/frames for the subcode is detected. A buffer manager monitors the contents of the buffer and counts the data and subcode components through separate counters. The buffer manager releases the data component and the subcode component to a host from the buffer when synchronization of the data component and the subcode component is detected.

Abstract: A technique for forming integrated circuit device contacts includes the formation of nitride spacers along side gate electrodes for LDD definition. In addition, a nitride cap layer is formed over the gate electrodes. When a contact opening is formed through the interlevel oxide dielectric, the nitride cap and sidewall spacers protect the gate electrode from damage and shorting. A highly doped poly plug is formed in the opening to make contact to the underlying substrate. Metalization is formed over the poly plug in the usual manner.

Abstract: The present invention relate to a device of protection against voltage gradients of a monolithic component including a vertical MOS power transistor and logic circuits. The protection circuit has an N-type substrate corresponding to the drain of the MOS transistor, and logic components being realized in at least one P-type well formed in the upper surface of the substrate. Each of the N-type regions connected to the ground of the logic circuit, or to a node of low impedance with respect to the ground, is in series with a resistor.

Abstract: An electronic system provides direct access between a first device and a decoder/encoder and a memory. The electronic system can be included in a computer in which case the memory is a main memory. Direct access is accomplished through one or more memory interfaces. Direct access is also accomplished in some embodiments by direct coupling of the memory to a bus, and in other embodiments, by direct coupling of the first device and decoder/encoder to a bus. The electronic system includes an arbiter for determining access for the first device and/or the decoder/encoder to the memory for each access request. The arbiter may be monolithically integrated into a memory interface of the decoder/encoder or the first device. The decoder may be a video decoder configured to decode a bit stream formatted to comply with the MPEG-2 standard. The memory may store predicted images which are obtained from a single preceding image and may also store intra images.

Abstract: A process of manufacturing cross-point matrix memory devices which have floating gate memory cells having the source channel self-aligned to the bit line and the field oxide is disclosed. The process includes the steps of growing a thin layer of tunnel oxide on the matrix region; depositing a stack structure comprising a first conductive layer, an intermediate dielectric layer, and a second conductive layer; photolithographing with a Poly1 mask to define a plurality of parallel floating gate regions in the stack structure; self-aligned etching of the stack structure, above the active areas, to define continuous bit lines; and implanting, to confer predetermined conductivity on the active areas. Advantageously, the self-aligned cascade etching step for removing parallel strips from multiple layers, down to the active areas of the substrate, is discontinued before the field oxide is removed, and the implantation step is carried out in the presence of field oxide over the source active areas.

Abstract: The present invention relates to a constant current generator including a reference voltage source providing a constant voltage with respect to a first ground; an operational amplifier receiving the constant voltage on a non-inverting input; and a follower transistor controlled by the output of the operational amplifier and connected between an input of a current mirror and a first resistor connected to the first ground. It further includes a second resistor connected between an output of the current mirror and a second ground, the output of the current mirror being also coupled to an inverting input of the operational amplifier; and a filtering circuit connected to reduce or eliminate, in the output signal of the operational amplifier, any high frequency ac component with respect to the first ground.