Patents Assigned to STMicroelectronics
  • Fully-dielectric-isolated FET technology
    Patent number: 5981318
    Abstract: A field-effect transistor structure wherein a single patterned thin film semiconductor layer: is monocrystalline, and epitaxially matched to and dielectrically isolated from an underlying body region, in channel locations; and is polycrystalline in source/drain locations which abut said channel locations.
    Type: Grant
    Filed: December 18, 1997
    Date of Patent: November 9, 1999
    Assignee: STMicroelectronics, Inc.
    Inventor: Richard A. Blanchard
  • Fully differential voltage-current converter
    Patent number: 5978240
    Abstract: A fully differential voltage-current converter, comprising a differential operational amplifier which is supplied with a differential voltage to be converted into a current, a first transistor being fedback to a noninverting input of the amplifier, a second transistor being fedback to an inverting input of the amplifier, the second transistor having the opposite polarity with respect to the first transistor, a third transistor and a fourth transistor having mutually opposite polarities being connected between a supply voltage and ground and to the second transistor in order to force a current that flows through the second transistor to be equal to a current that flows through the first transistor, a gate terminal of the first transistor being connected to a gate terminal of the fourth transistor.
    Type: Grant
    Filed: October 5, 1998
    Date of Patent: November 2, 1999
    Assignee: STMicroelectronics S.r.l.
    Inventor: Germano Nicollini
  • Method for forming an aluminum contact
    Patent number: 5976969
    Abstract: A method for forming an aluminum contact through an insulating layer includes the formation of an opening. A barrier layer is formed, if necessary, over the insulating layer and in the opening. A thin refractory metal layer is then formed over the barrier layer, and aluminum deposited over the refractory metal layer. Proper selection of the refractory metal layer and aluminum deposition conditions allows the aluminum to flow into the contact and completely fill it. Preferably, the aluminum is deposited over the refractory metal layer without breaking vacuum.
    Type: Grant
    Filed: June 27, 1997
    Date of Patent: November 2, 1999
    Assignee: STMicroelectronics, Inc.
    Inventors: Yih-Shung Lin, Fu-Tai Liou
  • Circuit and method for determining optimal phase combination for startup of a polyphase DC motor
    Patent number: 5977734
    Abstract: A circuit for determining an initial winding combination for motor startup of a polyphase dc motor having a transistor driver circuit comprising a plurality of high side winding drivers and low side winding drivers operably connected to first and second voltage sources comprises a current mirror circuit and a plurality of sense FETs each operably connected between one of the voltage sources and the gate of one of the winding driver transistors in each phase combination. The sense FETs are operably connected to one side of the current mirror circuit. The mirror circuit compares the current through the sense FET with a current threshold provided on the other side of the current mirror and produces an output signal when the threshold is reached. At the same time, the time to reach the threshold is measured and the phase combination having the longest time is stored.
    Type: Grant
    Filed: September 9, 1998
    Date of Patent: November 2, 1999
    Assignee: STMicroelectronics, Inc.
    Inventors: Li-Hsin David Lu, Chinh Dac Nguyen, Francis Yu
  • Current biased mode control circuit
    Patent number: 5977817
    Abstract: A circuit device for selecting operating modes using a single reference pin that uses current rather than voltage in an electronic subsystem. An operating mode is selected by modulating the input bias current over a range of values. A specific range is associated with a given function so that a value of current can assume a parametric input into the subsystem. The circuit has widespread application since current can be modulated faster than voltage and it eliminates the need for multiple voltage reference points.
    Type: Grant
    Filed: October 31, 1997
    Date of Patent: November 2, 1999
    Assignee: STMicroelectronics, Inc.
    Inventor: Axel Alegre de la Soujeole
  • Method of forming isolated regions of oxide
    Patent number: 5977607
    Abstract: A method is provided for forming isolated regions of oxide of an integrated circuit, and an integrated circuit formed according to the same. A pad oxide layer is formed over a portion of a substrate. A first silicon nitride layer is formed over the pad oxide layer. A polysilicon buffer layer is then formed over the first silicon nitride layer. A second silicon nitride layer is formed over the polysilicon layer. A photoresist layer is formed and patterned over the second silicon nitride layer. An opening is etched through the second silicon nitride layer and the polysilicon buffer layer to expose a portion of the first silicon nitride layer. A third silicon nitride region is then formed on at least the polysilicon buffer layer exposed in the opening. The first silicon nitride layer is etched in the opening. A field oxide region is then formed in the opening.
    Type: Grant
    Filed: May 23, 1995
    Date of Patent: November 2, 1999
    Assignee: STMicroelectronics, Inc.
    Inventors: Robert Louis Hodges, Frank Randolph Bryant, Fusen E. Chen, Che-Chia Wei
  • Non-volatile integrated low-doped drain device with partially overlapping gate regions
    Patent number: 5977586
    Abstract: A non-volatile integrated device having first and second dimensionally different polysilicon gate layers separated by an oxide layer for hot-carrier reliability. More specifically, the oxide and second polysilicon gate layer are selectively etched to form a second gate region over the first polysilicon gate layer that electrically contacts the first polysilicon gate in one direction and is isolated by the oxide in the other direction. Insulating sidewalls are formed over the first polysilicon gate layer regions that are not electrically contacted by the second gate layer to help isolate the second polysilicon gate and form an LDD structure within the substrate for the device.
    Type: Grant
    Filed: May 31, 1995
    Date of Patent: November 2, 1999
    Assignee: STMicroelectronics S.r.l.
    Inventors: Giuseppe Crisenza, Cesare Clementi
  • Adaptive optical sensor
    Patent number: 5978025
    Abstract: An integrated image processing system includes an array of cells arranged in rows and columns. Each cell corresponds to a pixel of an image and includes a photosensitive element for detecting the luminous intensity of its respective pixel and for generating a value. A first switch controls the transfer of the value from a respective photosensitive element to the corresponding capacitor, which stores the value. A second switch couples each of the cells in parallel to a common line. A control circuit receives the values from each cell on the common line and generates a signal for regulating the switching time interval of the first switch.
    Type: Grant
    Filed: November 20, 1996
    Date of Patent: November 2, 1999
    Assignee: STMicroelectronics S.r.l.
    Inventors: Alfredo Tomasini, Gianluca Colli, Ernestina Chioffi, Danilo Gerna
  • Shift level circuit for a high side driver circuit
    Patent number: 5977811
    Abstract: A translator circuit for a drive circuit of a power transistor connected to an electric load. The translator circuit includes a first current generator placed between a supply voltage reference and an input terminal of the drive circuit, a controlled switch placed between the input terminal and a ground reference, and a second current generator interposed between the controlled switch and the ground reference. The translator circuit further includes a circuit leg in the form of a current mirror connected in parallel with the second current generator. The translator circuit avoids phenomena of false switching.
    Type: Grant
    Filed: July 15, 1997
    Date of Patent: November 2, 1999
    Assignee: STMicroelectronics S.r.l.
    Inventor: Antonio Magazzu
  • Localization of defects of a metallic layer of a semiconductor circuit
    Patent number: 5976898
    Abstract: A method for locating possible defects on an opaque layer deposited on a production wafer of a semiconductor circuit, consisting in locally radiating an upper surface of the wafer by means of a laser, and detecting the occurrence of a current in a diode constituted by a PN junction placed under the opaque layer to be examined.
    Type: Grant
    Filed: December 20, 1996
    Date of Patent: November 2, 1999
    Assignee: STMicroelectronics S.A.
    Inventors: Michel Marty, Alain Brun
  • Sequential access memories
    Patent number: 5978295
    Abstract: A sequential access memory comprises N register elements each storing an information bit. These N register elements are divided into P groups each comprising L elements. In a first phase of operation whose duration corresponds to P-1 consecutive periods of the clock signal, only the last elements of each group are activated and are furthermore series-connected. In a second phase of operation whose duration corresponds to a single period of the clock signal, all the elements are activated simultaneously, the groups of elements being furthermore series-connected. The advantage is that it enables a reduction in the dynamic consumption of the memory.
    Type: Grant
    Filed: June 30, 1998
    Date of Patent: November 2, 1999
    Assignee: STMicroelectronics S.A.
    Inventors: Alain Pomet, Bernard Plessier
  • Radio frequency power MOSFET device having improved performance characteristics
    Patent number: 5977588
    Abstract: A power MOSFET suitable for use in RF applications and a method for making the same is disclosed. The power MOSFET has an increased distance between gate and drain regions of the device in order to decrease the device gate to drain capacitance C.sub.gd. The distance between the gate and drain regions is increased by selective doping of a polysilicon layer of the gate to produce at least two polysilicon gate regions separated by a region of undoped polysilicon that is positioned over a substantial portion of the drain region that resides between the channel portions of the body region of the device. The addition of a contact oxide layer formed directly above the region of undoped polysilicon further increases the distance between gate and drain. Finally, a metal layer is deposited over the entire structure to form the gate and source electrodes of the device.
    Type: Grant
    Filed: October 31, 1997
    Date of Patent: November 2, 1999
    Assignee: STMicroelectronics, Inc.
    Inventor: Viren C. Patel
  • Circuit for the generation of voltage for the programming or erasure of a memory that uses floating-gate transistors
    Patent number: 5978268
    Abstract: A voltage circuit generates a programming or erasure voltage for programming or erasing a floating-gate memory. The voltage generator circuit includes a charge pump to provide a pumped voltage and a shaping circuit to provide the programming or erasing voltage from the pumped voltage. A switching circuit enables the pumped voltage to reach a sufficient level before the shaping circuit generates the programming or erasure voltage.
    Type: Grant
    Filed: October 27, 1998
    Date of Patent: November 2, 1999
    Assignee: STMicroelectronics S.A.
    Inventors: Sebastien Zink, David Naura
  • Method and apparatus for driving an electroluminescent lamp
    Patent number: 5977720
    Abstract: An electroluminescent lamp is driven by a driving circuit that can supply an approximately sinusoidal signal, a bi-directional sawtooth signal or a single-ended sawtooth signal. Switches selectively transfer energy from a battery to an inductor and then from the inductor to the lamp. In one embodiment, the lamp voltage is compared to a reference waveform, such as a sinusoid. The switches are activated responsive to the error between the lamp voltage and reference waveform to minimize the error. The lamp can thus be driven with a closer approximation of the reference waveform.
    Type: Grant
    Filed: August 26, 1997
    Date of Patent: November 2, 1999
    Assignee: STMicroelectronics, Inc.
    Inventors: Ermanno Pace, Giorgio Mariani, Alessandro Fasan
  • Dual port SRAM cell having pseudo ground line or pseudo power line
    Patent number: 5973985
    Abstract: Disclosed is a multiport SRAM cell. The cell state may be switched by controlling the potential on a single bit line only. A true dual port SRAM cell (in which the two ports may be accessed nearly simultaneously without needing peripheral arbitration logic) employs two cross-coupled inverters, two bit lines, two word lines, and two access transistors. The SRAM cells employ internal "pseudo inverters" that can be independently powered on and off. By powering one of them off during the write operation, the internal conflict associated with changing the value of a stored bit is avoided. Each pseudo inverter may be powered on and off via a pseudo ground or a pseudo Vdd line which controls the potential to locations where ground or Vdd are normally supplied to CMOS inverters.
    Type: Grant
    Filed: August 11, 1998
    Date of Patent: October 26, 1999
    Assignee: STMicroelectronics, Inc.
    Inventor: Richard J. Ferrant
  • Method of forming a planar isolation structure in an integrated circuit
    Patent number: 5972776
    Abstract: A method is provided for forming isolated regions of oxide of an integrate circuit, and an integrated circuit formed according to the same. A plurality of active areas is formed in an upper surface of a portion of a substrate body. A field oxide region is formed which separates at least two of the plurality of the active areas, wherein an upper surface of the field oxide region is substantially planar with an upper surface of the substrate body. Nitride spots are formed in the bulk of the field oxide region and not in the active area which do not need to be removed since they do not effect device integrity.
    Type: Grant
    Filed: December 22, 1995
    Date of Patent: October 26, 1999
    Assignee: STMicroelectronics, Inc.
    Inventor: Frank Randolph Bryant
  • Control circuit with adjustable standby oscillator
    Patent number: 5973617
    Abstract: A control circuit adapted to be switched to a standby mode during periods without control requirement and to be repeatedly reset during the standby mode of operation for a short wake-up period each to a full mode of operation. The control circuit comprises a standby oscillator that is operative also in the standby mode and that is adjusted during wake-up periods.
    Type: Grant
    Filed: May 6, 1997
    Date of Patent: October 26, 1999
    Assignee: STMicroelectronics GmbH
    Inventors: Hans Reichmeyer, Francesco Colandrea
  • Differential input stage for wideband reception with high rejection of common mode
    Patent number: 5973515
    Abstract: An integrated circuit comprises at least one differential input stage. The differential input stage includes an input circuit and a shaping circuit. The input circuit comprises a first portion and a second portion for providing two pairs of differential signals. The propagation times of the first and second circuit portions are preferably substantially identical. The shaping circuit differentiates each of the two pairs of differential signals and combines them to obtain a single binary type of signal.
    Type: Grant
    Filed: June 12, 1998
    Date of Patent: October 26, 1999
    Assignee: STMicroelectronics S.A.
    Inventors: Roland Marbot, Pascal Couteaux, Anne Pierre Duplessix, Reza Nezamzadeh, Jean-Claude Le Bihan, Michel D'Hoe, Francis Mottini
  • Solid state capacitive switch
    Patent number: 5973623
    Abstract: A fingertip-operated solid state capacitance switch detects a capacity change that is induced by the physical contact of an ungrounded fingertip to an external dielectric surface of the solid state switch. The input and output of a solid state signal-inverting amplifier are respectively connected to two relatively large and ungrounded capacitor plates that are associated with, but electrically isolated from, the switch's external dielectric surface. An ungrounded fingertip forms a third capacitor plate on the switch's external surface. The solid state amplifier detects the presence of a fingertip on the switch's external surface by way of a change in capacitance within a compound, three plate, capacitor that includes the two ungrounded capacitor plates and the ungrounded fingertip that is resident on the switch's external surface.
    Type: Grant
    Filed: October 21, 1997
    Date of Patent: October 26, 1999
    Assignee: STMicroelectronics, Inc.
    Inventors: Bhusan Gupta, Alan Henry Kramer
  • Input structure for analog or digital associative memories
    Patent number: 5973949
    Abstract: An input structure for associative memories, including an array of elementary cells, a number of input lines, a number of output lines, a number of address lines, and a number of enable lines. Each elementary cell is formed by a D flip-flop having a data input coupled to one of the address lines and an enable input coupled to one of the enable lines, and by a switch coupled between an input line and an output line, and having a control input coupled to the output of a respective latch to selectively couple the respective input line and output line according to the data stored in the latch.
    Type: Grant
    Filed: September 30, 1997
    Date of Patent: October 26, 1999
    Assignee: STMicroelectronics S.r.l.
    Inventors: Alan Kramer, Roberto Canegallo, Mauro Chinosi, Giovanni Gozzini, Pier Luigi Rolandi, Marco Sabatini