Abstract: A generator circuit for a reference voltage independent of temperature variations uses a Brokaw cell biased by a current generator. The generator circuit includes a start-up circuit for delivering a current to the load of the generator using a transistor from the power-on instant until the switching on of the Brokaw cell and the consequent switching-off of the transistor. The circuit further includes a first field effect transistor having a gate coupled to a bandgap voltage node of the Brokaw cell and operatively connected in series with at least one diode between a biasing current generator of the start-up circuit and ground. The circuit also includes a second bipolar junction transistor having a base coupled to the power supply node of the Brokaw cell and operatively connected to a load resistance that is, in turn, connected to the supply rail and to the output transistor of the Brokaw cell for supplying current to the load during the start-up phase.

Abstract: The present invention relates to a digital-to-analog converter having a plurality of inputs for digital signals and an output for an analog signal. It comprises a current amplification circuit having an input and an output coupled to the converter output, and a plurality of floating gate MOS transistors corresponding to the plurality of converter inputs and having their source terminals coupled together and to a first reference of potential. The converter has drain terminals coupled together and to the input of the amplification circuit, and has control terminals coupleable, under control from the inputs of the plurality, to different references of potential having selected fixed values.

Abstract: An integrated circuit package with a path of high thermal conductivity is disclosed. A thermally conductive slug, formed of a material such as copper, is attached to an underside portion of a substrate, such as a printed circuit board or a ceramic substrate, through which an opening has been formed. An integrated circuit chip is mounted to one side of the slug exposed in the opening. An opposing surface of the slug lies below the plane of the underside of the substrate. The chip is wire bonded to the substrate, and is encapsulated in the conventional manner. Solder balls are attached to a portion of the underside of the substrate not covered by the slug in a ball-grid-array manner, for mounting to a circuit board. Upon mounting to the circuit board, a path of high thermal conductivity is provided between the chip and the circuit board, through the slug and the solder balls.

Abstract: A memory device comprising a semiconductor material substrate with a dopant of a first type, a first semiconductor material well with a dopant of a second type formed in the substrate; a second semiconductor material well with a dopant of the first type formed in the first well, an array of memory cells formed within the second well. Each memory cell comprises a first electrode and a second electrode respectively formed by a first and a second doped regions with dopant of the second type formed in the second well, and a control gate electrode.

Abstract: A precision oscillator includes a capacitor, a charging current source, a discharging current source, a switch for alternatingly connecting the capacitor to the charging current source and the discharging current source, and a hysteretic comparator connected to the capacitor for producing an oscillating signal responsive to charging and discharging the capacitor. The oscillator may also preferably include a duty cycle controller connected to at least one of the charging current source and the discharging current source for setting the charging current and/or the discharging current to thereby set a duty cycle of the oscillating signal by setting a ratio of the charging and discharging currents. The charging current source may have a current setting input for permitting setting of a charging current to the capacitor, and the discharging current source may have a current setting input for permitting setting of a discharging current from the capacitor.

Abstract: In a device for programming EPROM-Flash type memory cells of memory words of a memory, a bit line of a memory cell of a given rank of the first word and at least one bit line of a memory cell of the same rank in a word that is horizontally adjacent to this first word are connected together to two common programming connections by means of a bias circuit, and the bias circuit comprises two bias voltage inputs and one bias voltage output. The programming method consists in the successive programming, during different programming cycles, of the different cells of this first word and, during the same programming cycle, a different cell, of the same rank, in at least one word that is different from this first word is programmed.

Abstract: The video memory requisite of an MPEG decoder effecting a decompression of the I, P and optionally also of the B picture according to the MPEG compression algorithm and requiring the storing in respective buffers organized in said video memory of the respective MPEG-decompressed data, may be dynamically reduced by subsampling and recompressing according to a ADPCM algorithm of at least the data pertaining to the I and P pictures before coding and storing them in the respective buffers. Subsequently, the stored data are decoded, decompressed and upsampled for reconstructing blocks of pels to be sent to a macroblock-to-raster scan conversion circuit.

Abstract: A semiconductor device includes first through fourth pads and first through third external connection leads with the first external connection lead being a ground connection lead and the first and second pads being ground pads. First through fourth connection wires selectively connect the pads to the external connection leads. Additionally, a first ground line is connected to the first pad, a second ground line is connected to the second pad, a first protective diode connects the first ground line to the third pad, and a second protective diode connects the second ground line to the fourth pad. The first external connection lead is connected to the first pad via the first connection wire and to the second pad via the second connection wire, the third connection wire connects the third pad to the second external connection lead, and the fourth connection wire connects the fourth pad to the third external connection lead.

Abstract: A circuit for the generation of a high ramp voltage for the supply of voltage to a capacitive load, in particular a high voltage for the programming or erasure of at least one memory cell of a non-volatile memory, comprises floating-gate transistors as storage elements. This generation circuit comprises a P type load transistor connected by its source to the output of a voltage booster delivering a high direct and constant voltage (HIV), by its drain to the load, the high ramp voltage being available at this drain, and by its control gate to a control feedback circuit to control the load current. This circuit achieves automatic control over the slope of the high ramp voltage (Vpp). Application to the generation of a high ramp voltage whose slope is smaller than a critical slope and the maximum value is high.

Abstract: In a high density memory, such as a SRAM, DRAM, EPROM or EEPROM, a hierarchical bitline configuration is utilized such that a number of local bitlines are connected to a master bitline through interface circuitry which connects a local bitline to the master bitline. Local select signals, when set to the appropriate voltage level, couple a local bitline to the master bitline. In addition to reducing the local bitline capacitance that must be driven by memory cells, the hierarchical configuration may provide layout area savings as well. Interface circuitry is modified to provide voltage and signal gain and/or provide isolation between the local bitlines and the master bitlines, thereby reducing the amount of capacitance which must be driven by memory cells and the amount of time required to develop differential signals on the master bitlines.

Abstract: The invention relates to a self-regulated equalizer of the type which comprises a load circuit placed between first and second voltage references and having an input terminal which is connected to a modulated supply line, itself connected to the first voltage reference through a voltage step-up block placed between the first voltage reference and the modulated supply line and synchronized by a precharge enable signal received on a control terminal.

Abstract: A method for planarizing integrated circuit topographies, wherein, after a first layer of spin-on glass is deposited, a layer of low-temperature oxide is deposited before a second layer of spin-on glass.

Abstract: A load transient compensator and method of operating the load transient compensator for reducing the transient response time to a load capable of operating at either of several consumption levels when the load changes its power consumption level. The load transient compensator has a comparator having an output connected to an input of an upper driver and of a lower driver with the output of each of the driver being connected to a gate of a power transistor. When the load is in sleep mode and is about to start being accessed, the upper driver is turned on to turn on its associated transistor to supply additional current to the load, regulated by the comparison circuit. When the load is in the power up mode and it is about to stop being accessed, the lower driver is turned on to turn on its associated transistor to drain current supplied to the load by a supply, regulated by the comparison circuit.

Abstract: Disclosed is an electrical technique for clamping the bitline voltage above zero volts in a DRAM circuit. The technique may be used in embedded DRAM arrays implemented in logic-based technology employing low threshold voltages. The invention employs a low voltage generator to provide a bitline voltage slightly above zero volts. Applying this slightly elevated level to the input of a DRAM cell access transistor effectively increases the threshold voltage of that transistor and thus limits sub-threshold leakage current. The low voltage generator may be implemented as a cascode circuit with supplemental current sources.

Abstract: According to the present invention, entry into the test mode of an integrated circuit device is possible even when there is no device pin dedicated to a test mode function. Test mode control circuitry allows a pin of the integrated circuit device to be double mapped to a normal operation function and to a test mode function. The test mode control circuitry has a polarity circuit having a polarity bond pad and a fuse circuit having a fuse element, either of which may determine when the polarity of the pin is representative of a test mode function. Either down-bonding the polarity bond pad to the lead frame of the integrated circuit device or blowing the fuse renders the pin representative of the test mode function. Additionally, once the test mode of the device is entered, the device may be adequately stress tested.

Abstract: Disclosed is a method and associated apparatus for compensating for kTC noise in individual pixels of an MOS imaging array. The kTC noise at issue forms when a pixel is disconnected from a reset voltage by turning off an MOS transistor which controls access to the pixel photodiode. Compensation is accomplished by first exposing the photodiode to the reset voltage and then disconnecting the well region from V.sub.dd to cause it to float. By allowing the well to float, the kTC charge subsequently introduced (at the conclusion of the reset process) redistributes so that most of it accumulates on the capacitor between the well and the substrate. Later, the well is reclamped to V.sub.dd, and the noise contribution stored in the well-substrate capacitor is canceled. A disclosed apparatus includes an array of pixels, each having a separate well. In addition, access of the well to a source of power (V.sub.dd) must be switchable. Therefore, a transistor is included at each pixel's connection to a V.sub.dd.

Abstract: A variable capacitor in a semiconductor device is described in which the capacitance is varied by the movement of a dielectric material in the space between the plates of the capacitor in response to an external stimulus. A method of making such a variable capacitor is also described in which the capacitor is built in a layered structure with the top layer including a portion of dielectric material extending into the space between the capacitor plates. After formation of the top layer, an intermediate layer is etched away to render the top layer flexible to facilitate movement of the dielectric material in the space between the capacitor plates.

Abstract: A compensated voltage regulator of the type used in programming non-volatile memory cells of a memory cell matrix that is divided into sectors. The voltage regulator includes a comparator that is connected to a supply voltage. A first input terminal of the comparator is supplied a reference voltage, and a second input terminal is feedback connected to a program line. The control terminal of an output transistor is connected to an output terminal of the comparator, and a conduction terminal of the output transistor is connected to the memory cells by the program line. An output current is passed through a conduction terminal of the output transistor. Further, a compensation circuit is powered by the supply voltage. An input of the compensation circuit is connected to the output terminal of the comparator and to the output transistor, and an output of the compensation circuit is also connected to the output terminal of the comparator.

Abstract: A sense amplifier circuit for a semiconductor memory device comprises first current/voltage conversion means for converting a current of a memory cell to be read into a voltage signal, second current voltage/conversion means for converting a reference current into a reference voltage signal, and voltage comparator means for comparing the voltage signal with the reference voltage signal. The sense amplifier circuit comprises capacitive decoupling means for decoupling the voltage signal from the comparator means, and means for providing the capacitive decoupling means with an electric charge suitable for compensating an offset voltage introduced in the voltage signal by an offset current superimposed on the current of the memory cell to be read.

Abstract: A photodiode structure augmented with active area photosensitive regions is used for detecting impinging radiation. The photodiode includes a semiconductor base layer doped with impurities of a first carrier type, a field oxide layer disposed upon the base layer with an opening formed therethrough, a plurality of auxiliary oxide layers wherein each is separately disposed upon the base layer, and a semiconductor diffusion layer doped with impurities of a second carrier type arranged upon the base layer and in contact with the oxide layers. When the photodiode is electrically energized, a plurality of integral photosensitive regions is created within the depletion region to facilitate the detection of impinging radiation at an increased quantum efficiency.