Abstract: A semiconductor image sensor includes a plurality of pixels. Each pixel of the sensor includes a semiconductor substrate having opposite front and back sides and laterally delimited by a first insulating wall including a first conductive core insulated from the substrate, electron-hole pairs being capable of forming in the substrate due to a back-side illumination. A circuit is configured to maintain, during a first phase in a first operating mode, the first conductive core at a first potential and to maintain, during at least a portion of the first phase in a second operating mode, the first conductive core at a second potential different from the first potential.

Abstract: A bridge rectifier is formed by a first transistor coupled between a regulator output and a first tap, a second transistor coupled between the regulator output and a second tap, a third transistor coupled between the first tap and ground, and a fourth transistor coupled between the second tap and ground. A first comparator circuit, when enabled, compares ground to a voltage at the first tap and asserts a first low-side control signal to turn on the third transistor when the voltage at the first tap is below ground, and, when reset, samples an offset of the first comparator circuit. A second comparator circuit, when enabled, compares ground to a voltage at second first tap and asserts a second low-side control signal to turn on the fourth transistor when the voltage at the second tap is below ground, and, when reset, samples an offset of the second comparator circuit.

Abstract: A sense amplifier enable signal and a tracking signal are generated in response to an indication that a sufficient voltage difference has developed across bit lines of a memory. The sense amplifier enable signal has a pulse width between a leading edge and a trailing edge. The sense amplifier enable signal is propagated along a first U-turn signal line that extends parallel to rows of the memory array and is coupled to sense amplifiers arranged in a row to generate a sense amplifier enable return signal. The tracking signal is propagated along a second U-turn signal line extending parallel to columns of the memory array to generate a tracking return signal. The sense amplifier enable return signal and the tracking return signal are logically combined to generate a reset signal. Timing of the trailing edge of the pulse width is controlled by the reset signal.

Abstract: A circuit configured to sense an input analog signal generated by a sensor at a first frequency and to generate an output digital signal indicative of the sensed input analog signal. The circuit includes a conditioning circuit, an ADC, a feedback circuit, and a low-pass filter. The conditioning circuit is configured to receive the input analog signal and to generate a conditioned analog signal. The ADC is configured to provide a converted digital signal based on the conditioned analog signal. The feedback circuit includes a band-pass filter configured to selectively detect a periodic signal at a second frequency higher than the first frequency and to act on the conditioning circuit to counter variations of the periodic signal at the second frequency. The low-pass filter is configured to filter out the periodic signal from the converted digital signal to generate the output digital signal.

Abstract: A voltage level shifter device an input stage and an output stage. The input stage is configured to lower one of the first and second output terminals to the low level according to the level of the input voltage. A latch circuit includes a first branch having a first PMOS transistor and a second PMOS transistor coupled in series coupled between a shifted-high-level voltage supply terminal and the first output terminal and a second branch having a third PMOS transistor an a fourth PMOS transistor coupled in series between the shifted-high-level voltage supply terminal and the second output terminal. The first output terminal is a gate of the second PMOS transistor and to a gate of the third PMOS transistor. The second output terminal is coupled a gate of the fourth PMOS transistor and to a gate of the first PMOS transistor.

Abstract: An integrated circuit includes a polysilicon region that is doped with a dopant. A portion of the polysilicon region is converted to a polyoxide region which includes un-oxidized dopant ions. A stack of layers overlies over the polyoxide region. The stack of layers includes: a first ozone-assisted sub-atmospheric pressure thermal chemical vapor deposition (O3 SACVD) TEOS layer; and a second O3 SACVD TEOS layer; wherein the first and second O3 SACVD TEOS layers are separated from each other by a dielectric region. A thermally annealing is performed at a temperature which induces outgassing of passivation atoms from the first and second O3 SACVD TEOS layers to migrate to passivate interface charges due to the presence of un-oxidized dopant ions in the polyoxide region.

Abstract: The present disclosure is directed to arranging user data memory cells and test memory cells in a configurable memory array that can perform both differential and single ended read operations during memory start-up and normal memory use, respectively. Different arrangements of the user data memory cells and the test memory cells in the memory array result in increased effectiveness of memory array, in terms of area optimization, memory read accuracy and encryption for data security.

Abstract: In providing electrical wire-like connections between at least one semiconductor die arranged on a semiconductor die mounting area of a substrate and an array of electrically-conductive leads in the substrate, pressure force is applied to the electrically-conductive leads in the substrate during bonding the wire-like connections to the electrically-conductive leads. Such a pressure force is applied to the electrically-conductive leads in the substrate via a pair of mutually co-operating force transmitting surfaces. These surfaces include a first convex surface engaging a second concave surface.

Abstract: An integrated physical unclonable function device includes at least one reference capacitor and a number of comparison capacitors. A capacitance determination circuit operates to determine a capacitance of the at least one reference capacitor and a capacitance of each comparison capacitor. The determined capacitances of the comparison capacitors are then compared to the determined capacitance of the reference capacitor by a comparison circuit. A digital word is then generated with bit values indicative of a result of the comparisons made by the comparison circuit.

Abstract: A strain gauge includes first and second substrates spaced apart from one another. A first flexible printed circuit board portion is in contact with a top side of the first and second substrates, and has a first Wheatstone bridge formed therein. The first flexible printed circuit board portion positions the first Wheatstone bridge such that two resistors of the first Wheatstone bridge are positioned to span from the top side of the first substrate to the top side of the second substrate. A second flexible printed circuit board portion is in contact with a bottom side of the first and second substrates, and has a second Wheatstone bridge formed therein. The second flexible printed circuit board positions the second Wheatstone bridge such that two resistors of the second Wheatstone bridge are positioned to span from the bottom side of the first substrate to the bottom side of the second substrate.

Abstract: A DC-DC converter includes: an transformer having a primary winding and a secondary winding magnetically coupled to the primary winding; a power oscillator applying an oscillating signal to the primary to transmit a power signal to the secondary winding; a rectifier connected to the secondary winding of the transformer to obtain an output DC voltage by rectification of the power signal; comparison circuitry to generate an error signal representing a difference between the output DC voltage and a reference voltage; a transmitter connected to the secondary winding of the transformer to apply an amplitude modulation to the power signal at the secondary winding of the transformer in response to the error signal to thereby produce an amplitude modulated signal at the primary winding; and a receiver and control circuit connected to the primary winding to control an amplitude of the oscillating signal as a function of the amplitude modulated signal.

Abstract: An integrated optical sensor is formed by a pinned photodiode. A semiconductor substrate includes a first semiconductor region having a first type of conductivity located between a second semiconductor region having a second type of conductivity opposite to the first type one and a third semiconductor region having the second type of conductivity. The third semiconductor region is thicker, less doped and located deeper in the substrate than the second semiconductor region. The third semiconductor region includes both silicon and germanium. In one implementation, the germanium within the third semiconductor region has at least one concentration gradient. In another implementation, the germanium concentration within the third semiconductor region is substantially constant.

Abstract: An optical testing circuit on a wafer includes an optical input configured to receive an optical test signal and photodetectors configured to generate corresponding electrical signals in response to optical processing of the optical test signal through the optical testing circuit. The electrical signals are simultaneously sensed by a probe circuit and then processed. In one process, test data from the electrical signals is simultaneously generated at each step of a sweep in wavelength of the optical test signal and output in response to a step change. In another process, the electrical signals are sequentially selected and the sweep in wavelength of the optical test signal is performed for each selected electrical signal to generate the test data.

Abstract: Various embodiments provide an optical lens that includes wafer level diffractive microstructures. In one embodiment, the optical lens includes a substrate, a microstructure layer having a first refractive index, and a protective layer having a second refractive index that is different from the first refractive index. The microstructure layer is formed on the substrate and includes a plurality of diffractive microstructures. The protective layer is formed on the diffractive microstructures. The protective layer provides a cleanable surface and encapsulates the diffractive microstructures to prevent damage and contamination to the diffractive microstructures. In another embodiment, the optical lens includes a substrate and an anti-reflective layer. The anti-reflective layer is formed on the substrate and includes a plurality of diffractive microstructures.

Abstract: A current-generator circuit includes an output-current generator circuit having a control branch to be coupled to a control current generator and adapted to provide a control current pulse and a driver electrically coupled between the control branch and the output leg. A compensation circuit includes a first compensation branch configured to generate a compensation current pulse that is a function of the control current pulse and a second compensation branch coupled in a current mirror configuration with the first compensation branch to receive the compensation current pulse. The second compensation branch includes a resistive block having an electrical resistance that is a function of a resistance of an output load. The second compensation branch is electrically coupled to the control branch and the driver is electrically coupled to the control branch and to the output leg.

Abstract: In at least one embodiment, a Geiger-mode avalanche photodiode, including a semiconductor body, is provided. The semiconductor body includes a semiconductive structure and a front epitaxial layer on the semiconductive structure. The front epitaxial layer has a first conductivity type. An anode region having a second conductivity type that is different from the first conductivity type extends into the front epitaxial layer. The photodiode further includes a plurality of gettering regions in the semiconductive structure.

Abstract: A bridge driver circuit applies a bias voltage across first and second input nodes of a resistive bridge circuit configured to measure a physical property such as pressure or movement. A sensing circuit senses a bridge current that flows through the resistive bridge circuit in response to the applied bias voltage. A temperature dependent sensitivity of the resistive bridge circuit is determined by processing the sensed bridge current. A voltage output at first and second output nodes of the resistive bridge circuit is processed to determine a value of the physical property. This processing further involves applying a temperature correction in response to the determined temperature dependent sensitivity.

Abstract: An integrated circuit chip includes a front face having an electrical connection pad. An overmolded encapsulation block encapsulates the integrated circuit chip and includes a front layer at least partially covering a front face of the integrated circuit chip. A through-hole the encapsulation block is located above the electrical connection pad of the integrated circuit chip. A wall of the through-hole is covered with an inner metal layer that is joined to the front pad of the integrated circuit chip. A front metal layer covers a local zone of the front face of the front layer, with the front metal layer being joined to the inner metal layer to form an electrical connection. The inner metal layer and the front metal layer are attached or anchored to activated additive particles that are included in the material of the encapsulation block.

Abstract: A single photon avalanche diode (SPAD) has a cathode coupled to a high voltage supply and an anode coupled to a first node. A photodetection circuit includes: a first n-channel transistor having a drain coupled to the first node, a source coupled to ground, and a gate coupled to a third node; a second n-channel transistor having a drain coupled to the first node, a source coupled to ground, and a gate coupled to a second node; and an inverter having an input coupled to the first node and an output coupled to an intermediate node. A current starved inverter has an input coupled to the intermediate node and an output coupled to the second node, a logic gate has inputs coupled to the intermediate node and the second node, and an output coupled to the third node.

Abstract: A method of operating an electronic device includes generating scramble control codes. The scramble codes are generated by generating a random number, shifting the random number to produce a shifted random number, generating control signals by selecting different subsets of the shifted random number, and generating scramble control words by selecting different subsets of the random number based upon the control signals. The method further includes receiving a password comprised of sub-words and scrambling those sub-words according to the scramble control codes, retrieving a verification word comprised of sub-words and scrambling those sub-words according to the scramble control codes, and comparing the scrambled sub-words of the password to the scrambled sub-words of the verification word to thereby authenticate an external device that provided the password.