Abstract: A method begins with forming a first wiring layer on a substrate, forming a cavity in the substrate, and laminating a bottom side of the substrate so as to cover a bottom side of the cavity. Next, an integrated circuit is placed within the cavity of the substrate, and then a first optically transparent layer is disposed on the top surface of the substrate to cover a top surface of the integrated circuit. The first optically transparent layer has an aperture formed therein exposing at least a portion of the top surface of the integrated circuit. A second wiring layer is disposed on a top surface of the first optically transparent layer in a pattern that does not obstruct light traveling to or from the top surface of the integrated circuit. The integrated circuit is a laser emitting integrated circuit or a reflected light detector.

Abstract: A first generator produces a first signal that is supplied to an energy storage circuit. Energy transfer circuitry coupled to the energy storage circuit transfers energy stored in the energy storage circuit to an output node. A driver circuit coupled to the energy transfer circuitry switches the energy transfer circuitry between a state where energy from the first signal is stored in the energy storage circuit and a state where energy stored in the energy storage circuit section is delivered to the output node. A voltage at the energy storage circuit varies between an upper value and a lower value around a voltage setting point. A second generator, which is a scaled-down replica of the first generator, produces a second signal that is indicative of an open-circuit voltage of the first generator. The driver circuit uses the second signal to set the voltage setting point.

Abstract: A PWM signal generator circuit includes a multiphase clock generator that generates a number n of phase-shifted clock phases having the same clock period and being phase shifted by a time corresponding to a fraction 1/n of the clock period. The PWM signal generator circuit determines for each switch-on duration first and second integer numbers, and for each switch-off duration third and fourth integer numbers. The first integer number is indicative of the integer number of clock periods of the switch-on duration and the second integer number is indicative of the integer number of the additional fractions 1/n of the clock period of the switch-on duration. The third integer number is indicative of the integer number of clock periods of the switch-off duration, and the fourth integer number is indicative of the integer number of the additional fractions 1/n of the clock period of the switch-off duration.

Abstract: A power stage in an electronic fuse circuit is driven by controller. The controller includes a first comparator set for output voltage control and a second comparator set for output current control. Each comparator set includes at least one comparator having a reference input, a feedback input, and one or more outputs. A driver circuit includes output terminals for driving the power stage. The driver circuit includes a switch that is selectively activated in response to outputs from the first and second comparator sets to clamp the voltage across the output terminals of the driver circuit. The clamp operation is made in response to feedback input to either of the first and second comparator sets having exceeded a certain reference.

Abstract: A high-to-low voltage interface circuit includes a differential circuit stage with a differential amplifier circuit having inverting and non-inverting inputs coupled to first and second input pads as well as a differential output having first and second output nodes. A pair of bias amplifier stages sensitive to the common mode voltage of the differential amplifier circuit are arranged in first and second current mirror paths from the first and second input pads to the inverting/non-inverting inputs of the differential amplifier circuit, respectively. The bias amplifier stages are configured to maintain the first input pad and the second input pad of the differential circuit stage at the common mode voltage.

Abstract: An optical waveguide is configured to propagate a light signal. Metal vias are arranged along and on either side of a portion of the optical waveguide. Additional metal vias are further arranged along and on either side of the optical waveguide both upstream and downstream of the portion of the optical waveguide. The metal vias and additional metal vias are oriented orthogonal to a same plane, the same plane being orthogonal to a transverse cross-section of the portion of the optical waveguide.

Abstract: In an embodiment, A device includes an operational amplifier and a feedback loop. The feedback loop is coupled between a first input of the operational amplifier and an output of the operational amplifier. The feedback loop is controllable according to a saturation of the operational amplifier. In one example, the device is incorporated in a microcontroller.

Abstract: A substrate includes a first solid semiconductor region and a second semiconductor on insulator region. First and second cavities are simultaneously formed in the first and second regions, respectively, of the substrate using etching processes in two steps which form an upper portion and a lower portion of each cavity. The first and second cavities will each have a step at a level of an upper surface of the insulator of the second semiconductor on insulator region. A further oxidation of the first cavity produces a rounded or cut-off area for the upper portion.

Abstract: Cantilever probes are produced for use in a test apparatus of integrated electronic circuits. The probes are configured to contact corresponding terminals of the electronic circuits to be tested during a test operation. The probe bodies are formed of electrically conductive materials. On a lower portion of each probe body that, in use, is directed to the respective terminal to be contacted, an electrically conductive contact region is formed having a first hardness value equal to or greater than 300 HV; each contact region and the respective probe body form the corresponding probe.

Abstract: A differential pair of transistors receives input voltages. Current mirror transistors and cascode transistors are coupled to the differential pair of transistors. The differential pair of transistors is coupled between the cascode transistors and a tail transistor that draws a first bias current from a tail node, the first bias current having a magnitude equal to a product of a total bias current and a constant that is less than one. A first current source transistor draws a second bias current from a node between the differential pair and cascode transistors so the second bias current bypasses one transistor of the differential pair of transistors. The second bias current has a magnitude equal to a product of the total bias current and a value equal to one minus the constant. An output stage is biased by an output at node between the cascode transistors and the current mirror transistors.

Abstract: A quantizer generates a thermometer coded signal from an analog voltage signal. Data weighted averaging (DWA) of the thermometer coded signal is accomplished by controlling the operation of a crossbar switch controlled by a switch control signal to generate an output DWA signal. The output DWA signal is latched to generate a latched output DWA signal which is processed along with bits of the thermometer coded input signal in feedback loop to generate the switch control signal. The latching of the output DWA signal is performed in an input register of a digital-to-analog converter which operates to convert the latched output DWA signal to a feedback analog voltage from which the analog voltage signal is generated. The switch control signal specifies a bit location for a beginning logic transition of the output DWA signal cycle based on detection of an ending logic transition of the latched DWA signal.

Abstract: A pixel includes a photosensitive circuit, a sense node, a first transistor and a first capacitor. A first electrode of the first capacitor is connected to a control terminal of the first transistor. A second electrode of the first capacitor is to a node of application of a first control signal.

Abstract: A pixel includes a photoconversion zone, an insulated vertical electrode and at least one charge storage zone. The photoconversion zone belongs to a first part of a semiconductor substrate and each charge storage zone belongs to a second part of the substrate physically separated from the first part of the substrate by the insulated vertical electrode.

Abstract: A method for manufacturing an electronic chip includes providing a semiconductor layer located on an insulator covering a semiconductor substrate. First and second portions of the semiconductor layer are oxidized up to the insulator. Stresses are generated in third portions of the semiconductor layer, and each of the third portions extend between two portions of the semiconductor layer that are oxidized. Cavities are formed which extend at least to the substrate through the second portions and the insulator. Bipolar transistors are formed in at least part of the cavities and first field effect transistors are formed in and on the third portions. Phase change memory points are coupled to the bipolar transistors.

Abstract: An in-memory compute (IMC) device includes a compute array having a first plurality of cells. The compute array is arranged as a plurality of rows of cells intersecting a plurality of columns of cells. Each cell of the first plurality of cells is identifiable by its corresponding row and column. The IMC device also includes a plurality of computation engines and a plurality of bias engines. Each computation engine is respectively formed in a different one of a second plurality of cells, wherein the second plurality of cells is formed from cells of the first plurality. Each computation engine is formed at a respective row and column intersection. Each bias engine of the plurality of bias engines is arranged to computationally combine an output from at least one of the plurality of computation engines with a respective bias value.

Abstract: A device operate by alternating between first and second phases of operation. The device includes a first transistor and a first circuit. The first circuit operates to: couple a first conduction terminal of the first transistor to an output node of the device and a second conduction terminal of the first transistor to a first node of application of a potential during each first phase; and couple the first terminal of the first transistor to a second node of application of a potential and the second conduction terminal of the first transistor to the output node during each second phase of operation.

Abstract: A time-of-flight ranging system includes an array of single photon avalanche diode (SPAD) pixels, and control circuitry that causes the array of SPAD pixels to integrate SPAD event data received from each SPAD pixel of a first cluster of SPAD pixels during a first illumination of a target, the first cluster of SPAD pixels being a subset of the array of SPAD pixels, and integrate SPAD event data received from each SPAD pixel of a second cluster of SPAD pixels during a second illumination of the target, the second cluster of SPAD pixels being a subset of the array of SPAD pixels. At a start of integration of the SPAD event data received from each SPAD pixel of the second cluster of SPAD pixels, the integrated SPAD event data that was received from each SPAD of the first cluster of SPAD pixels is accumulated.

Abstract: A capacitive element is located in an active region of the substrate and on a front face of the substrate. The capacitive element includes a first electrode and a second electrode. The first electrode is formed by a first conductive region and the active region. The second electrode is formed by a second conductive region and a monolithic conductive region having one part covering a surface of said front face and at least one part extending into the active region perpendicularly to said front face. The first conductive region is located between and is insulated from the monolithic conductive region and a second conductive region.

Abstract: A data demodulating circuit includes a sensing circuit sensing a power signal applied to a coil at first and second times, and outputting an analog value representing a difference in voltage of the power signal at the first and second times. An analog-to-digital converter digitizes the analog value output by the analog voltage differential sensing circuit to produce a digital code. A compensation circuit, over a period of time, compares a present value of the digital code to a first value of the digital code during the period, and subtracts a given value from the present value of the digital code if the present value is greater than the first value but add the given value to the present value of the digital code if the present value is less than the first value. An accumulator accumulates output of the compensation circuit, and a filter filters output of the accumulator.

Abstract: A drive signal is applied to a MEMS gyroscope having several intrinsic resonant modes. Frequency and amplitude of mechanical oscillation in response to the drive signal is sensed. At startup, the drive signal frequency is set to a kicking frequency offset from a resonant frequency corresponding to a desired one of the intrinsic resonant modes. In response to sufficient sensed amplitude of mechanical oscillation at the kicking frequency, a frequency tracking process is engaged to control the frequency for the drive signal to sustain mechanical oscillation at the frequency of the desired one of the plurality of intrinsic resonant modes as the oscillation amplitude increases. When the increasing amplitude of the mechanical oscillation exceeds a threshold, a gain control process is used to exercise gain control over the applied drive signal so as to cause the amplitude of mechanical oscillation to match a further threshold. At that point start-up terminates.