Patents Assigned to STMicroelectronics
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Patent number: 12144077Abstract: An LED lighting system includes switching circuitry adjustably driving a string of LEDs and being controlled by a reference current and an enable signal. A controller generates the reference current and enable signal based upon a PWM signal such that the switching circuitry: sources a first LED current to the string of LEDs that is proportional to a duty cycle of the PWM signal when the duty cycle is greater than a threshold duty cycle to thereby perform analog dimming; and sources a second LED current to the string of LEDs that has a duty cycle proportional to the duty cycle of the PWM signal when the duty cycle of the PWM signal is less than the threshold duty cycle, such that an average LED current delivered to the string of LEDs is proportional to the duty cycle of the PWM signal to thereby perform digital dimming.Type: GrantFiled: September 30, 2021Date of Patent: November 12, 2024Assignee: STMicroelectronics S.r.l.Inventors: Giovanni Gritti, Claudio Adragna
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Patent number: 12142938Abstract: An over-voltage protection circuit and methods of operation are provided. In one embodiment, a method includes monitoring a voltage at an output of a rectifier, a voltage at an output of a voltage regulator, or a combination thereof. The method further includes determining the over-voltage condition based on the monitoring; and in response to determining the over-voltage condition, regulating the voltage at the output of the rectifier in accordance with a voltage difference between the voltage at the output of the rectifier and the voltage at the output of the voltage regulator.Type: GrantFiled: January 15, 2024Date of Patent: November 12, 2024Assignee: STMicroelectronics Asia Pacific Pte Ltd.Inventor: Yannick Guedon
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Patent number: 12140483Abstract: A calibration method of a temperature sensor is provided. The temperature sensor having a current source and a ring oscillator generating a square pulse signal with a temperature-dependent square pulse frequency. The acquisition of a first square pulse frequency measurement at a first temperature from the square pulse signal forms a first measurement point. A second square pulse frequency measurement at a second temperature from the second square pulse signal forms a second measurement point. The determination of the relation data being representative of an affine relation between square pulse frequency measurements and temperatures. The affine relation being defined by a used proportionality coefficient modified with respect to a measured proportionality coefficient of a measured affine relation linking the first measurement point and the second measurement point.Type: GrantFiled: October 25, 2021Date of Patent: November 12, 2024Assignee: STMicroelectronics (Rousset) SASInventors: Vincent Binet, Bruno Gailhard
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Patent number: 12140799Abstract: A ring resonator electro-optical device includes a first silicon nitride waveguide and a second annular silicon waveguide that comprises a first section running under a second section of the first waveguide. The second waveguide also includes an annular silicon strip having a cross-section increasing in the first section from a minimum cross-section located under the second section.Type: GrantFiled: September 15, 2021Date of Patent: November 12, 2024Assignee: STMicroelectronics (Crolles 2) SASInventors: Patrick Le Maitre, Nicolas Michit
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Patent number: 12142552Abstract: A lead frame for an integrated electronic device includes a die pad made of a first metallic material. A top coating layer formed by a second metallic material is arranged on a top surface of the die pad. The second metallic material has an oxidation rate lower than the first metallic material. The top coating layer leaves exposed a number of corner portions of the top surface of the die pad. A subsequent heating operation, for example occurring in connection with wirebonding, causes an oxidized layer to form on the corner portions of the top surface of the die pad at a position in contact with the top coating layer.Type: GrantFiled: November 28, 2022Date of Patent: November 12, 2024Assignee: STMicroelectronics S.r.l.Inventor: Fulvio Vittorio Fontana
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Patent number: 12144187Abstract: A method for manufacturing an electronic chip includes providing a semiconductor layer located on an insulator covering a semiconductor substrate. First and second portions of the semiconductor layer are oxidized up to the insulator. Stresses are generated in third portions of the semiconductor layer, and each of the third portions extend between two portions of the semiconductor layer that are oxidized. Cavities are formed which extend at least to the substrate through the second portions and the insulator. Bipolar transistors are formed in at least part of the cavities and first field effect transistors are formed in and on the third portions. Phase change memory points are coupled to the bipolar transistors.Type: GrantFiled: June 15, 2023Date of Patent: November 12, 2024Assignee: STMicroelectronics (Crolles 2) SASInventors: Remy Berthelon, Olivier Weber
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Patent number: 12143015Abstract: In an embodiment a switching power supply includes a voltage ramp generator comprising at least one output capacitor, wherein the generator is configured such that the output capacitor has a first value during a first operating cycle of a first operating mode and a second value during subsequent operating cycles of the first operating mode.Type: GrantFiled: April 27, 2022Date of Patent: November 12, 2024Assignee: STMICROELECTRONICS (ROUSSET) SASInventor: Sebastien Ortet
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Patent number: 12139396Abstract: A microelectromechanical sensor device has a detection structure including: a substrate having a first surface; a mobile structure having an inertial mass suspended above the substrate at a first area of the first surface so as to perform at least one inertial movement with respect to the substrate; and a fixed structure having fixed electrodes suspended above the substrate at the first area and defining with the mobile structure a capacitive coupling to form at least one sensing capacitor. The device further includes a single monolithic mechanical-anchorage structure positioned at a second area of the first surface separate from the first area and coupled to the mobile structure, the fixed structure, and the substrate and connection elements that couple the mobile structure and the fixed structure mechanically to the single mechanical-anchorage structure.Type: GrantFiled: July 23, 2021Date of Patent: November 12, 2024Assignee: STMICROELECTRONICS S.r.l.Inventors: Francesco Rizzini, Carlo Valzasina, Gabriele Gattere
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Patent number: 12142536Abstract: A semiconductor substrate includes a buried semiconductor layer and semiconductor wells. A device for detecting a possible thinning of the semiconductor substrate via the rear face thereof is formed on and in the semiconductor wells. The device is a non-inverting buffer including an input terminal and an output terminal, the device being powered between a supply terminal and a reference terminal where the buried semiconductor layer provides the supply terminal. A control circuit delivers an input signal in a first state to the input terminal and outputs a control signal indicating a detection of a thinning of the substrate if a signal generated at the output terminal in response to the input signal is in a second state different from the first state.Type: GrantFiled: December 15, 2022Date of Patent: November 12, 2024Assignee: STMicroelectronics (Rousset) SASInventors: Alexandre Sarafianos, Abderrezak Marzaki
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Patent number: 12140714Abstract: A waveform generator includes a system control unit and signal channels controlled by the system control unit and configured to supply driving signals for driving a respective transducer of an array of transducers. Each signal channel includes a sequential access memory having rows, where each row contains an instruction word configured to generate a respective step of a waveform to be generated. A memory output of the sequential access memory is defined by an output row at a fixed location. The waveform to be generated is defined by a block of instruction words. Each signal channel also includes an internal control unit that is configured to sequentially move the content of the sequential access memory, based on the instruction word currently at the memory output, so that sequences of instruction words are provided at the output row.Type: GrantFiled: February 16, 2021Date of Patent: November 12, 2024Assignee: STMicroelectronics S.r.l.Inventors: Stefano Passi, Roberto Giorgio Bardelli, Anna Moroni
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Publication number: 20240367610Abstract: A method of performing an authentication process to authenticate an electric motor unit includes establishing, by an external controller, secure encrypted communication with motor electronics of the electric motor unit, and sending, by the external controller, an authentication request to the motor electronics over the secure encrypted communication. The method further includes receiving, by the external controller, an authentication response from the motor electronics, verifying, by the external controller, a motor of the electronic motor unit as an authorized part based on the authentication response, and enabling control of the motor by the external controller only after successful authentication.Type: ApplicationFiled: July 16, 2024Publication date: November 7, 2024Applicant: STMicroelectronics International N.V.Inventors: Subodh Vikram SHUKLA, Saurabh SONA
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Publication number: 20240372359Abstract: The present description concerns a device of protection against electrostatic discharges including: at least one first rectifying element including an anode connected to a first terminal and a cathode connected to a first node of the device; at least one second rectifying element including an anode connected to a second node of the device and a cathode connected to the first terminal; and at least one Zener diode or at least one Shockley diode series-connected with a capacitive element between the first and second nodes.Type: ApplicationFiled: April 22, 2024Publication date: November 7, 2024Applicant: STMicroelectronics International N.V.Inventors: Jérôme HEURTIER, Fabrice GUITTON, Eric LACONDE
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Publication number: 20240370547Abstract: According to one aspect, a method for recording biometric data of a holder on a card including a microcontroller configured to communicate via a secure communication channel with a remote server comprising an account linked to the card holder, the method comprising: authenticating the holder on an application of a device configured to communicate with said server and said card, then authenticating the server by the card via the secure communication channel by means of the application of said device, then recording the biometric data of the holder by a fingerprint reader of the card controlled by the microcontroller of the card if the server is authenticated by the card.Type: ApplicationFiled: December 29, 2023Publication date: November 7, 2024Applicant: STMicroelectronics International N.V.Inventors: Frederic GOUABAU, Frederic PIQUET
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Publication number: 20240372541Abstract: Provided is a time interleaving circuit to mitigate glitches. A first loading stage outputs first data representative of first serialized data. A second loading stage generates second serialized data. The second loading stage receives the first data output by the first loading stage. In response to the first data having a first state, the time interleaving circuit inverts the second serialized data to generate second data representative of the second serialized data. In response to the first data having a second state, the time interleaving circuit outputting the second data without inverting the second serialized data. Exclusive disjunction logic receives the second data and operates on the first data and the second data to generate output data.Type: ApplicationFiled: July 17, 2024Publication date: November 7, 2024Applicant: STMicroelectronics International N.V.Inventor: Aradhana KUMARI
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Publication number: 20240371738Abstract: A packaged semiconductor device includes a substrate having a first surface and a second surface opposite the first surface. At least one semiconductor die is mounted at the first surface of the substrate. Electrically-conductive leads are arranged around the substrate, and electrically-conductive formations couple the at least one semiconductor die to selected leads of the electrically-conductive leads. A package molding material is molded onto the at least one semiconductor die, onto the electrically-conductive leads and onto the electrically-conductive formations. The package molding material leaves the second surface of the substrate uncovered by the package molding material. The substrate is formed by a layer of electrically-insulating material.Type: ApplicationFiled: July 16, 2024Publication date: November 7, 2024Applicant: STMicroelectronics S.r.l.Inventor: Roberto TIZIANI
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Patent number: 12134556Abstract: A semiconductor device includes: a substrate; a transduction microstructure integrated in the substrate; a cap joined to the substrate and having a first face adjacent to the substrate and a second, outer, face; and a channel extending through the cap from the second face to the first face and communicating with the transduction microstructure. A protective membrane made of porous polycrystalline silicon permeable to aeriform substances is set across the channel.Type: GrantFiled: November 23, 2021Date of Patent: November 5, 2024Assignees: STMICROELECTRONICS S.R.L., STMicroelectronics International N.V.Inventors: Enri Duqi, Lorenzo Baldo, Paolo Ferrari, Benedetto Vigna, Flavio Francesco Villa, Laura Maria Castoldi, Ilaria Gelmi
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Patent number: 12136883Abstract: An active flyback converter is transitioned between a plurality of operational states based on a comparison of a control voltage signal to voltage thresholds and a count of a number of consecutive switching cycles during which a clamp switch is kept off. The plurality of operational states includes a run state, an idle state, a first burst state, and a second burst state. Each set of consecutive switching cycles of the first burst state includes a determined number of switching cycles during which signals are generated to turn the power switch on and off and to maintain an off state of the clamp switch, and a switching cycle in a determined position in the set of switching cycles during which signals are sequentially generated to turn the power switch on, turn the power switch off, turn the clamp switch on and turn the clamp switch off.Type: GrantFiled: September 23, 2022Date of Patent: November 5, 2024Assignee: STMICROELECTRONICS S.r.l.Inventors: Claudio Adragna, Massimiliano Gobbi, Giuseppe Bosisio
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Patent number: 12136917Abstract: Provided is a voltage level shifter that operates in sub-threshold voltages. The level shifter includes a level shifting stage. The level shifting stage receives a first signal from a first voltage domain and outputs a second signal to a second voltage domain. The level shifter includes a first auxiliary stage. In response to the first signal having a first voltage level corresponding to a first logical state and a first node of the level shifting stage having a supply voltage level, the first auxiliary stage sources current to a second node of the level shifting stage. Sourcing the current to the second node accelerates a transition of the first node to a reference voltage. The level shifting stage outputs a second signal to a second voltage domain.Type: GrantFiled: January 6, 2023Date of Patent: November 5, 2024Assignee: STMicroelectronics International N.V.Inventors: Kallol Chatterjee, Rohit Kumar Gupta
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Patent number: 12135575Abstract: An AFSM core includes a destination state-cell generating a destination state-signal, and a source state-cell generating a source state-signal and causing transition of the source state-signal in response to an acknowledgement indicating transition of the destination state-signal. The acknowledgment is communicated through a delay. A state-overlap occurs between transition of the destination state-signal and transition of the source state-signal. An output-net includes a balanced logic-tree receiving inputs, including the destination state-signal, from the core, and an additional logic-tree cascaded with the balanced logic-tree to form an unbalanced logic-tree so an input to the additional logic-tree is provided by output from the balanced logic-tree and another input receives the source state-signal. Tree propagation time occurs between receipt of a transition in the destination state-signal by the balanced logic-tree and a resulting transition of the output from the balanced logic-tree.Type: GrantFiled: November 28, 2022Date of Patent: November 5, 2024Assignee: STMicroelectronics International N.V.Inventor: Roberta Priolo
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Patent number: 12136608Abstract: A multi-chip package including a first integrated circuit and a second integrated circuit. The first integrated circuit includes a first side having a first conductive layer, a second side having a second conductive layer, and an edge, the first conductive layer coupled to the second conductive layer at a location adjacent to the edge. The second integrated circuit is coupled to the second conductive layer of the first integrated circuit.Type: GrantFiled: February 9, 2023Date of Patent: November 5, 2024Assignee: STMICROELECTRONICS PTE LTDInventors: Yong Chen, David Gani