Abstract: A device includes global positioning circuitry, sensing circuitry, and processing circuitry. The global positioning circuitry, in operation, receives location-related data. The sensing circuitry, in operation, senses data related to the device. The processing circuitry, in operation, determines a motion state of the electronic system based on data sensed by the sensing circuitry, and selects a plurality of control parameters from one or more configuration matrixes based on the determined motion state. The plurality of control parameters includes a power-mode control parameter and a location-determination control parameter. The processing circuitry configures a power-mode of the device based on the power-mode control parameter, and determines a location characteristic of the device based on the received location-related data and the location-determination control parameter.

Abstract: Described herein is a lock system (e.g., for a vehicle door) including an NFC circuit in communication with a microcontroller that monitors the voltage of a battery (e.g., the vehicle battery). The microcontroller switches the NFC circuit to card emulation (CE) mode with energy harvesting capability when the battery voltage falls below a threshold so that the NFC circuit can harvest energy from a nearby Qi wireless charging field and store that harvested energy in an energy storage device. When the energy storage device is sufficiently charged, it is used power the microcontroller and an electronically actuated mechanical lock (e.g., vehicle door lock), then the microcontroller cooperates with the NFC circuit to switch the NFC circuit to NFC reader mode and attempt to verify a nearby NFC device. If the NFC device is verified, the microcontroller operates the lock, otherwise, it maintains the lock in an inactive state.

Abstract: An electronic device receives data including an application update module for an application program, the application update including a first part, the first part including first update information and an indication value. A processor of the electronic device then compares the first update information with reference information associated with the indication value and stored in a memory of the electronic device. The processor then installs a second part of the application update module when the first update information corresponds to the reference information, thereby producing an updated application program.

Abstract: A TRIAC features first and second main-terminal contacts, and a gate terminal contact, with multiple semiconductor regions stacked along a first-axis and extending laterally along an intersecting second-axis that defines first, second, and middle regions. The semiconductor regions include a third N-type region overlying the second main-terminal contact, a second P-type region overlying the second main-terminal contact, a second N-type region overlying the second P-type region, a first P-type region overlying the second N-type region, a first N-type region partially overlying the first P-type region, a fourth N-type region partially overlying the first P-type region, and a fifth N-type region partially overlying the first P-type region. The first main-terminal contact is partly on the first N-type region in the first region and on the first P-type region in the second region, while the gate terminal contact is partly on both the first P-type region and the fourth N-type region.

Abstract: A photodiode is formed in a semiconductor substrate of a first conductivity type. The photodiode includes a first region having a substantially hemispherical shape and a substantially hemispherical core of a second conductivity type, different from the first conductivity type, within the first region. An epitaxial layer covers the semiconductor substrate and buries the first region and core.

Abstract: A test circuit is configured to test and calibrate an impedance of a driver of an integrated circuit. Testing the impedance includes driving first and second currents through the driver via a first contact pad and a ground metallization of the integrated circuit. Testing the impedance includes measuring the voltage at a test metalization while driving the first and second current while the test metalization is successively coupled to the first contact pad and the ground metallization while driving the first and second test currents.

Abstract: A heterojunction power device includes: a substrate containing semiconductor material; a first active area and a second active area, arranged on the substrate symmetrically opposite with respect to an axis of symmetry and accommodating respective heterostructures; a separation region, extending along the axis of symmetry between the first active area and the second active area. The power device further includes: a first conductive bus configured to distribute a first electric potential of the power device in parallel to the first and the second active areas; a second conductive bus configured to distribute a second electric potential of the power device, different from the first electric potential, in parallel to the first and the second active areas. The first and the second conductive buses extend along the axis of symmetry above the separation region and the second conductive bus overlies the first conductive bus.

Abstract: An in-memory computation device performs a multiply-and-accumulate (MAC) operation. A computation array includes groups of memory cells coupled to a bitline, each group storing a computational weight and having a positive cell flowing a positive-cell current and a negative cell flowing a negative-cell current which are a function of a total current and the sign and absolute value of the respective computational weight. A row-activation circuit receives an input signal and provides, for each input value, during an elaboration interval, a positive-activation signal having a positive-activation duration and a negative-activation signal having a negative-activation duration, the durations being a function of an elaboration duration and of the sign and absolute value of the respective input value. A column-elaboration circuit samples bitline current and provides, in response thereto, at least one output signal.

Abstract: A HEMT device including: a semiconductor body forming a heterostructure; a gate region on the semiconductor body and elongated along a first axis; a gate metal region including a lower portion on the gate region and recessed with respect to the gate region, and a upper portion on the lower portion and having a width greater that the lower portion along a second axis; a source metal region extending on the semiconductor body and made in part of aluminum; a drain metal region on the semiconductor body, the source metal region and the drain metal region on opposite sides of the gate region; a first conductivity enhancement region of aluminum nitride, extending on the semiconductor body and interposed between the source metal region and the gate region, the first conductivity enhancement region being in direct contact with the source metal region and being separated from the gate region.

Abstract: The present disclosure is directed to accelerometer measurement compensation for a device with first and second accelerometers. The first and second accelerometers are included in first and second components, respectively, of the device that are configured to rotate with respect to a hinge. The device detects a stuck condition of the first accelerometer, and compensates acceleration measurements of the first accelerometer by exploiting redundant information from the second accelerometer and applying a runtime calibration of undesired offsets.

Abstract: An in-memory computation device performs a multiply-and-accumulate (MAC) operation. A computation array includes groups of memory cells coupled to a bitline, each group storing a computational weight and having a positive cell flowing a positive-cell current and a negative cell flowing a negative-cell current which are a function of a total current and the sign and absolute value of the respective computational weight. A row-activation circuit receives an input signal and provides, for each input value, during an elaboration interval, a positive-activation signal having a positive-activation duration and a negative-activation signal having a negative-activation duration, the durations being a function of an elaboration duration and of the sign and absolute value of the respective input value. A column-elaboration circuit samples bitline current and provides, in response thereto, at least one output signal.

Abstract: A sense amplifier circuit includes first, second inputs coupled to first, second memory sensing nodes, respectively. A sensing circuit operates to sense a differential signal between the first, second inputs. A first boosting capacitor has a first terminal coupled to the first input and a second terminal coupled to a switchable node. A second boosting capacitor has a first terminal coupled to the second input and a second terminal coupled to the switchable node. Control circuitry operates, responsive to a bitline boost activation signal having a first value, to couple the first terminals of the first, second boosting capacitors to a regulated supply voltage and drive the switchable node to ground. Responsive to the bitline boost activation signal having a second value, the first terminals of the first, second boosting capacitors are decoupled from the regulated supply voltage and the switchable node is driven to the regulated supply voltage.

Abstract: A random access memory (RAM) includes an array of arranged in rows and columns. The rows of the storage elements correspond to respective memory locations of the RAM. The storage elements of a row have a common gated-clock input and respective data inputs, and each row of the array of storage elements includes a plurality of D type latches. In operation, an address input of the RAM receives a memory address identifying a memory location in the RAM. Clock gating circuitry of the RAM, generates respective gated-clock signals for the rows of the array of storage elements based on the memory address received at the address input. Memory operation are performed using storage elements of the array based on the gated-clock signals.

Abstract: The present disclosure is directed to a fully analog voltage regulator circuit with reference modulation. The voltage regulator circuit includes a low-dropout regulator, a voltage-to-current convert, a resistor-capacitor filter circuit, and an operational amplifier voltage buffer. The voltage regulator circuit minimizes dropout voltage of the circuit by comparing the output voltage of the voltage regulator to a reference voltage and adjusting the output voltage of the op amp voltage buffer, accordingly. The voltage regulator circuit includes two operational amplifiers, wherein the negative input of a first of the two operational amplifiers is coupled to the negative input of a second of the two operational amplifiers through the resistor-capacitor filter circuit.

Abstract: An integrated circuit device includes a metal contact and a passivation layer extending on a sidewall of the metal contact and on first and second surface portions of a top surface of the metal contact. The passivation layer is format by a stack of layers including: a tetraethyl orthosilicate (TEOS) layer; a Phosphorus doped TEOS (PTEOS) layer on top of the TEOS layer; and a Silicon-rich Nitride layer on top of the PTEOS layer. The TEOS and PTEOS layers extend over the first surface portion, but not the second surface portion, of the top surface of the metal contact. The Silicon-rich Nitride layer extends over both the first and second surface portions, and is in contact with the second surface portion.

Abstract: A bidirectional PFC system includes a high-frequency branch with a first transistor connected between an IO node and a high-frequency tap, and a second transistor connected between the high-frequency tap and a reference node, and a low-frequency branch with a first thyristor connected between the IO node and a low-frequency tap, and a second thyristor connected between the low-frequency tap and the reference node. An inductor is connected between the first node and the high-frequency tap. A first capacitor is connected between the first node and the low-frequency tap. The first node and the low-frequency tap are coupled to input terminals. A control circuit generates first and second gate drive signals for the transistors so as to modify an AC signal at the input terminals such that the AC current falls below a holding current of the second thyristor prior to zero crossing of the AC voltage.

Abstract: A supply voltage detector of an integrated circuit is able to detect the state of a supply voltage upon startup with both high-speed and low overall power consumption. The supply voltage detector includes a comparator that generates an output voltage based on the current state of the supply voltage. The comparator includes a startup current booster that generates a supplemental current for the comparator while the supply voltage is ramping up. The start of current booster stops generating the supplemental current when the supply voltage reaches the expected steady-state value or a selected fraction or portion of the expected steady-state value.

Abstract: An in-memory computation (IMC) device is configured to receive input data and provide intermediate output data. A word line activation circuit receives input data and provides corresponding word line activation signals. A memory array includes memory cells in a matrix arrangement coupled to bit lines and to word lines. Each bit line is traversed by a respective bit line current depending on the memory cells connected to the bit line. Selectors each coupled to a respective part of the bit lines are configured to select one of the respective bit lines. A digital detector for each selector is electrically connected, through the respective selector, with the respective bit line selected. The digital detectors sample the respective bit line currents and, in response to the bit line currents, provide the respective intermediate output data.

Abstract: The present disclosure is directed to a flat no-lead semiconductor package with a surfaced mounted structure. An end portion of the surface mounted structure includes a recessed member so that the surface mounted structure is coupled to leads of the flat no-lead semiconductor package through, among others, the sidewalls of the recessed members.

Abstract: A microfluidic dispensing device has a plurality of chambers arranged in sequence, each having an inlet receiving a liquid to be dispensed and a nozzle for emitting a drop of liquid. An actuator in each chamber receives an actuation quantity and causes a drop of liquid to be emitted by the nozzle of the respective chamber. A drop emission detection element in each chamber generates an actuation command upon detecting the emission of a drop of liquid. A sequential activation electric circuit includes a plurality of sequential activation elements, one for each chamber, each coupled to the drop emission detection element of the respective chamber and to an actuator associated with a subsequent chamber in the sequence of chambers. Each sequential activation element receives the actuation command from the drop emission detection element associated with the respective chamber and activates the actuator associated with the subsequent chamber in the sequence of chambers.