Abstract: In embodiments, a system includes a first and a second processing unit, a memory, and a firewall device. The first processing unit operates in a secure mode and generates memory access requests having a secure level. The second processing unit operates in a non-secure mode and generates memory access requests having a non-secure level. The memory includes a first memory area that can be shared between the first and second processing units. The firewall device includes a first firewall circuit with a first configuration authorizing access to the first memory area in the presence of a secure or non-secure level access request. The firewall circuit includes a second configuration prohibiting access to the first memory area in the presence of a secure level access request and authorizing access to the first memory area only in the presence of a non-secure level access request.

Abstract: A method of corrupting contents of a memory array includes asserting a signal at a reset node to thereby cause starving of current supply to the memory array, and selecting bit lines and complementary bit lines associated with desired columns of the memory array that contain memory cells to have their contents corrupted. For each desired column, a logic state of its bit line and complementary bit line are forced to a same logic state. Each word line associated with desired rows of the memory array that contains memory cells to have their contents corrupted is simultaneously asserted, and then simultaneously deasserted to thereby place each memory cell to have its contents corrupted into a metastable state during a single clock cycle.

Abstract: An integrated circuit includes an output pad, and I/O driver that drives data to the output pad, and a predriver that controls the I/O driver. The integrated circuit includes maximum voltage generator that receives a first supply voltage and a second supply voltage and outputs to the predriver a maximum voltage corresponding to the higher of the first supply voltage and the second supply voltage.

Abstract: In accordance with an embodiment, an integrated circuit chip includes a first input configured to receive a rectified potential and a second input configured to receive a reference potential; a first circuit configured to maintain the rectified potential at a constant value on the first input; a second circuit having a power supply input coupled to the first node; a first resistor series-connected to the first circuit between the second input and the first node, or connected between the first input and the first node; a third circuit connected across the first resistor and configured to deliver a signal which is an image of a current in the first resistor; and a fourth circuit configured to determine a mains frequency and/or a mains voltage based at least on the signal which is the image of the current in the first resistor.

Abstract: The present disclosure is directed to a flat no-lead semiconductor package with a surfaced mounted structure. An end portion of the surface mounted structure includes a recessed member so that the surface mounted structure is coupled to leads of the flat no-lead semiconductor package through, among others, the sidewalls of the recessed members.

Abstract: The present disclosure relates to a method for protecting a first data item applied to a cryptographic algorithm, executed by a processor, wherein said algorithm is a per-round algorithm, with each round processing contents of first, second and third registers, the content of the second register being masked, during first parity rounds, by the content of a fourth register and the content of the third register being masked, during second parity rounds, by the content of a fifth register.

Abstract: The present disclosure relates to a method for authenticating instructions and operands in an electronic system comprising a controller. The method includes extracting instructions and operands via a first circuit of the controller from at least a first memory internal to the controller using a matrix bus of the controller, collecting, on the matrix bus, via a second circuit internal to the controller, instructions and operands during their transmission to the first circuit, and generating a word representative of the instructions and operands.

Abstract: In an embodiment, a USB interface includes a transformer, a primary winding of the transformer, and a first switch in series between a first and a second node, a secondary winding of the transformer and a component in series between a third and a fourth node, the fourth node configured to be set a first reference potential, a second switch connected between the third node and a first terminal, the first terminal configured to provide an output voltage of the USB interface; wherein the component is configured to avoid a current circulation in the secondary winding when the first switch is closed and a control circuit configured to compare a first voltage of an interconnection node between the secondary winding and the component to a first threshold and compare the first voltage to a second threshold when the first voltage is, in absolute values, above the first threshold.

Abstract: A device includes a memory and processing circuitry coupled to the memory. The processing circuitry, in operation, generates an indication of a predicted difference in a direction of arrival (DoA) of a signal using a trained autoregressive model. A predicted indication of a DoA of the signal is generated based on a previous indication of the DoA of the signal and the indication of the predicted difference in the DoA of the signal. The processing circuitry actuates or controls an antenna array based on predicted indications of the DoA of the signal.

Abstract: The present disclosure relates to a process to control an optoelectronic device comprising a single-photon avalanche diode n a substrate, wherein the diode comprises a first region doped with a first type of conductivity level with a first face of the substrate and a second region doped with a second type of conductivity extending from the first face to a second face of the substrate opposed to the first face, wherein the device comprises a third conducting or semiconducting region at the second face, wherein the process comprises the application of a biasing voltage to the third region in order to generate an electric field that accelerates the charges generated in the diode.

Abstract: A metasurface optic, designed for short-wave infrared (SWIR) range devices, is formed of one or more unit cells with a specific arrangement of truncated cone-shaped subwavelength nanostructures, tailored to achieve various optical functionalities. The one or more unit cells are formed from a design set selected from among multiple different design sets, each of the multiple different design sets featuring truncated cones having a unique combination of height (800 nm to 1100 nm), sidewall angle (91° to) 93°, and pitch (550 nm to 750 nm), with base radius values of the truncated cones within a given design set varying from 75 nm to 250 nm in 1 nm increments.

Abstract: A microelectromechanical accelerometer includes a microstructure, having sensing terminals and driving terminals distinct from the sensing terminals, a supporting body and a movable mass, coupled to the supporting body so as to be able to oscillate according to a sensing axis with respect to a rest position, and a control unit coupled to the microstructure so as to form a force feedback loop configured to maintain the movable mass in the rest position. The movable mass includes a sensing structure and a driving structure, respectively coupled to the sensing terminals and to the driving terminals through capacitive couplings variable as a function of displacements of the movable mass from the rest position. The sensing structure and the driving structure are electrically insulated and rigidly coupled with each other.

Abstract: A substrate of a lead frame is made of a first material. The substrate is covered by a barrier film made of a second material, different from the first material. The barrier film is then covered by a further film made of the first material. A first portion of the lead frame is encapsulated within an encapsulating body in a way which leaves a second portion of lead frame extending out from and not being covered by the encapsulating body. A first portion of the further film which is not covered by the encapsulating body is then stripped away to expose the barrier film at the second portion of the lead frame. A second portion of the further film is left remaining encapsulated by the encapsulating body. The exposed barrier film at the second portion of the lead frame is then covered with a tin or tin-based layer.

Abstract: A retention flip flop includes a first latch, a second latch, and a retention latch. The first and second latches are powered by an interruptible primary supply voltage while the retention latch is powered by a secondary supply voltage that is not interrupted. The retention flip-flop receives a single retention control signal that controls whether the flip-flop is in a standard mode or a retention mode. In the retention mode, the flip-flop clock signal is paused.

Abstract: A system includes a memory and a processor coupled to the memory. The processor executes an instruction set having a word size. The processor includes arithmetic processing circuitry, which, in operation, executes arithmetic operations on operands having the word size. The arithmetic processing circuitry includes an arithmetic logic circuit (ALU) having an operand size smaller than the word size of the instruction set. The ALU, in operation, generates partial results of the arithmetic operations. A multiplexing network coupled to inputs of the ALU provides portions of the operands to the ALU. A shift register having the word size of the instruction set accumulates partial results generated by the ALU over a plurality of clock cycles and outputs results of the arithmetic operations based on the accumulated partial results.

Abstract: A MEMS pressure transducer includes a semiconductor body, a lower dielectric region arranged above the semiconductor body, and a fixed electrode region and a lower anchoring region, which are formed by conductive material, are arranged on the lower dielectric region and are laterally separated from each other. A membrane of conductive material is suspended above the fixed electrode region so as to delimit a cavity upwardly, the fixed electrode region facing the cavity, the membrane being deformable as a function of pressure and forming a variable capacitor together with the fixed electrode region. An upper anchoring region of conductive material laterally delimits the cavity and is interposed, in direct contact, between the membrane and the lower anchoring region.

Abstract: A wireless charging and data transmission system that includes first and second half-bridges coupled in parallel between supply and ground nodes. Each half-bridge includes high-side and low-side transistors. A first high-side driving circuit drives the control terminal of the high-side transistor of the first half-bridge with a first bootstrap voltage at a first node, and a second high-side driving circuit drives the control terminal of the high-side transistor of the second half-bridge with a second bootstrap voltage at a second node. A charge pump circuit generates and maintains a master bootstrap voltage at a master node, which is equal to the voltage at the supply node plus a given voltage. A switch circuit couples the master node to the first node during the low-side conduction period of the first half-bridge and couples the master node to the second node during the low-side conduction period of the second half-bridge.

Abstract: An optical device includes at least a first optical component and a second optical component attached together with a first transparent adhesive film having at least two adhesive surfaces.

Abstract: An electronic device includes a semiconductor body of SiC having an upper surface and a lower surface opposite to each other along a first axis and including: a drain substrate extending into the semiconductor body starting from the bottom surface and with a first electrical conductivity type; a drift layer extending into the semiconductor body starting from the upper surface and with the first electrical conductivity type and a second dopant concentration; a body region accommodated in the drift layer; and a source region accommodated in the body region. The electronic device further includes a gate structure on the upper surface. The semiconductor body further comprises at least one doped pocket region which is buried in the drift layer, has a second electrical conductivity type and is aligned along the first axis with the source region and/or with the gate structure.

Abstract: SRAM cells are connected in columns by bit lines and connected in rows by first and second word lines coupled to first and second data storage sides of the SRAM cells. First the first word lines are actuated in parallel and then next the second word lines are actuated in parallel in first and second phases, respectively, of an in-memory compute operation. Bit line voltages in the first and second phases are processed to generate an in-memory compute operation decision. A low supply node reference voltage for the SRAM cells is selectively modulated between a ground voltage and a negative voltage. The first data storage side receives the negative voltage and the second data storage side receives the ground voltage during the second phase. Conversely, the second data storage side receives the negative voltage and the first data storage side receives the ground voltage during the first phase.