Abstract: The present description concerns a method or device wherein an untraceability feature of a first near-field communication device is deactivated by an action on a hardware switch.

Abstract: A clock recovery circuit comprises an input node receiving a data signal having a data rate, and a digital oscillator producing a local clock signal with a frequency higher than the data rate. A counter clocked by the local clock signal has its count value sampled and reset at the rising and falling edges of the data signal, and a storage block coupled to the counter stores a count value that is updated in response to the current sampled count value of the counter lying in an update range between lower and upper bounds. A threshold value set is produced as a function of the updated count value stored in the storage block. Sampling circuitry receives and samples the data signal, and provides a sampled version of the data signal in response to the count value of the counter reaching any of the threshold values.

Abstract: In an embodiment an envelope detection device includes an input terminal configured to receive an amplitude-modulated radio frequency signal, a first resistive element and a first MOS transistor connected in parallel between the input terminal and a first node configured to receive a reference potential, a first capacitive element connected between a gate of the first MOS transistor and the first node, an envelope detection circuit connected to the input terminal and configured to supply a voltage representative of an envelope of the amplitude-modulated signal and a circuit for controlling the first MOS transistor configured to supply a first current to the gate of the first MOS transistor only when the voltage is smaller than a first threshold and draw a second current from the gate of the first MOS transistor only when the voltage is higher than a second threshold, the second threshold being higher than the first threshold.

Abstract: A method for manufacturing an ohmic contact for a HEMT device, comprising the steps of: forming a photoresist layer, on a semiconductor body comprising a heterostructure; forming, in the photoresist layer, an opening, through which a surface region of the semiconductor body is exposed at said heterostructure; etching the surface region of the semiconductor body using the photoresist layer as etching mask to form a trench in the heterostructure; depositing one or more metal layers in said trench and on the photoresist layer; and carrying out a process of lift-off of the photoresist layer.

Abstract: A communication circuit supports a first communication protocol and a second communication protocol that is different from the first communication protocol. A number of signals include first signals conveying first information messages and second signals conveying second information messages. The first information messages include a repetitive message having fixed repeated content and the second information messages include a non-repetitive message having variable content. The first signals and the second signals are transmitted via the communication circuit using the first communication protocol for the first signals and the second communication protocol for the second signals.

Abstract: A method and apparatus for performing dynamic current scaling of an input current of a voltage regulator are provided. The method and apparatus allow tuning current consumption in various applications, calculating a duration of an activity phase in which various algorithms are executed and activating dynamic current scaling of a regulator if the activity duration is shorter than a programmable threshold. A controller receives a threshold for an activity duration and a window size in which to evaluate the activity duration.

Abstract: A multi-level pulser circuit comprises a set of first input pins for receiving respective positive voltage signals at different voltage levels, a set of second input pins for receiving respective negative voltage signals at different voltage levels, and a reference input pin configured to receive a reference voltage signal intermediate the positive voltage signals and the negative voltage signals. The circuit comprises an output pin configured to supply a pulsed output signal. The circuit further comprises control circuitry configured to selectively couple the output pin to one of the first input pins, the second input pins and the reference input pin to generate the pulsed output signal at the output pin.

Abstract: A control circuit includes: a flip-flop having an output configured to be coupled to a control terminal of a transistor and for producing a first signal; a comparator having an output coupled to an input of the flip-flop, and first and second inputs for receiving first and second voltages, respectively; a transconductance amplifier having an input for receiving a sense voltage indicative of a current flowing through the transistor, and an output coupled to the first input of the comparator; a zero crossing detection (ZCD) circuit having an input configured to be coupled to a first current path terminal of the transistor and to an inductor, where the ZCD circuit is configured to detect a demagnetization time of the inductor and produce a third signal based on the detected demagnetization time; and a reference generator configured to generate the second voltage based on the first and third signals.

Abstract: Test circuitry includes a scan-compressor receiving n scan-input bits from n input-pins and compressing those bits for distribution among z scan-chains, z being less than n. A scan-decompressor receives test response data from the scan-chains and decompresses the test response data, reconstructing n scan-output bits. An OCC generates a test-clock based on clock-bits received from a clock-chain, with the test-clock operating the scan-chains and the clock-chain. The clock-chain receives m clock-chain input bits from m of the input-pins, m being less than n, and provides the clock-bits to the OCC for generating the test-clock. The test circuitry performs tests on the IC. Each test is associated with the test-clock generated by the OCC based on a given set of clock-bits. Tests associated with the test-clock generated by the OCC based on the same given set of clock-bits are performed after a single loading of that same given set of clock-bits.

Abstract: A multi-level non-volatile memory cell has N levels, N being even and greater than two, corresponding respectively to N logical data that can be stored in the memory cell and to N corresponding read current ranges. A datum stored in the memory cell is read by performing successive comparisons of a read current output by the memory cell with reference currents selected from a set of N-1 reference currents having values respectively lying between two different successive ranges using a dichotomous algorithm starting with the reference current having the median value.

Abstract: A phase-change memory cell to be read is associated with a phase-change reference memory cell placed in a SET state. The reference memory cell has a structure that is identical to that of the memory cell. A first voltage is applied to the memory cell to cause output of a first current. A second voltage is applied to the reference memory cell to cause output of a second current. A sense amplifier is coupled to the memory cell and to the reference memory cell and is configured to compare respective values of the first current and of the second current and generate output information representative of the logic value of the datum stored by the memory cell.

Abstract: System, method, and circuitry for generating a linker model for use by a toolchain associated with a programmable computing device. One or more regions in the memory resources available to the programmable computing devices is defined for used by an application executing on the programmable computing device. One or more sections is defined for those regions for use by the application. Resource boundaries are generated for the application based on the defined regions and the defined sections. A user is enabled to modify the defined regions or the defined sections or the generated resource boundaries. A linker model is then generated based on the available memory resources, the defined regions, the defined sections, and the generated resource boundaries. This linker model is then utilized to generate a linker script for the programmable computing device based the linker syntax compatible with a toolchain linker for the programmable computing device.

Abstract: A phase change memory element includes a memory region, a first electrode and a second electrode. The memory region is arranged between the first and the second electrodes and is made of a GST alloy. An average percentage of germanium in the GST alloy is higher than 50%. The memory region has a storage portion formed by a GST alloy that includes nitrogen in an electrically relevant amount. The GST alloy of the storage portion has a percentage of germanium inclusively between 60% and 68%; a percentage of antimony inclusively between 9% and 5%; a percentage of tellurium inclusively between 18% and 10%; and a percentage of nitrogen inclusively between 5% and 25%.

Abstract: A crash detection system includes first and second sensors and a processor. The processor receives first sensor data output by the first sensor, determines whether the first sensor data indicates a first class or a second class, outputs an enable signal to the second sensor if the first sensor data indicates the second class, receives second sensor data output by the second sensor after the enable signal is output, determines whether the second sensor data indicates a high acceleration value, determines whether the first sensor data indicates the first class within a predetermined amount of time after the second sensor data is determined to indicate the high acceleration value, and outputs a signal indicating a crash has occurred in response to determining that the first sensor data indicates the first class within the predetermined amount of time after the second sensor data is determined to indicate the high acceleration value.

Abstract: A set of configuration memory locations store configuration data for a microcontroller unit. A hardware monitoring module is coupled by an interconnection bus to the configuration memory locations. The hardware monitoring module reads from an instruction memory a command including an address of a target memory location in the set of configuration memory locations. Data is read from the target memory location corresponding to the address read and a checksum value is computed as a function of the data that is read from the target memory location. The computed checksum value is then compared to a respective expected checksum value stored in a checksum storage unit. An alarm signal is triggered in response to a mismatch detected between the computed checksum value and the respective expected checksum value.

Abstract: An HEMT device, comprising: a semiconductor body including a heterojunction structure; a dielectric layer on the semiconductor body; a gate electrode; a drain electrode, facing a first side of the gate electrode; and a source electrode, facing a second side opposite to the first side of the gate electrode; an auxiliary channel layer, which extends over the heterojunction structure between the gate electrode and the drain electrode, in electrical contact with the drain electrode and at a distance from the gate electrode, and forming an additional conductive path for charge carriers that flow between the source electrode and the drain electrode.

Abstract: A wireless power receiver includes a rectifier with first and second inputs coupled to first and second terminals of a receiver coil, and having a first output coupled to ground and a second output at which a rectified voltage is produced. A first switch is coupled between the second input and ground, and is controlled by a first gate voltage generated at a first node. A second switch is coupled between the first node and ground, and is controlled by a second gate voltage. The first gate voltage closes the first switch to couple the second input to ground when the rectified voltage is less than a threshold voltage, boosting the rectified voltage. The second gate voltage closes the second switch to cause the second gate voltage to be pulled to ground when the rectified voltage is greater than the threshold voltage, limiting the boosting of the rectified voltage.

Abstract: In an embodiment a DC to DC conversion circuit includes a DC to DC converter connected to an input path and an output path and a current limiting circuit including a circuit configured to detect when an input or output current of the DC to DC converter exceeds or falls below a current threshold and a controller configured to store a first voltage level of an output voltage of the DC to DC converter in response to the input or output current exceeding the current threshold, to store a second voltage level of the output voltage in response to the input or output current falling below the current threshold and to set a control signal based on the first and second voltage levels.

Abstract: In an embodiment a non-volatile memory cell includes a substrate, a first body in the substrate, a second body in the substrate, a first storage transistor having a first conduction region and a second conduction region in the first body, the first and second conduction regions delimiting a first channel region in the first body, a first control gate region in the second body, an insulating region overlying the substrate, a single floating gate region extending on the substrate and embedded in the insulating region, the single floating gate region having a first portion on the first body and a second portion on the second body, the first portion and second portion being connected and electrically coupled, a first selection via extending through the insulating region and electrically coupling the first conduction region with a first conduction node, a second selection via extending through the insulating region and electrically coupling the second conduction region with a second conduction node and a first con

Abstract: According to an embodiment, a method for testing a triple-voting flop (TVF) is provided. The method includes providing a first and a second scan enable signal by a control circuit to, respectively, a first scan flip-flop and a third scan flip-flop of the TVF; receiving a third scan enable signal at the second scan flip-flop of the TVF; providing a scan input signal to the first scan flip-flop, the second scan flip-flop, and the third scan flip-flop; controlling the first scan enable signal, the second scan enable signal, and the third scan enable signal; receiving, at an output of the TVF, a scan output signal; and determining whether the TVF suffers from a fault based on the scan output signal and the controlling of the first scan enable signal, the second scan enable signal, and the third scan enable signal.