Abstract: The present disclosure is directed to an optical sensor package with light shielding material covering five sides. The optical sensor package includes a transparent layer, a substrate layer, sensor elements between the transparent layer and the substrate layer, a solder mask on the side of the substrate layer opposite the transparent layer, and layer of molding material covering five sides of the optical sensor package. The solder mask and layer of molding material prevent light from entering the sides of the optical sensor package or from traveling through the substrate layer and reflecting toward the sensor elements.

Abstract: A semiconductor die is arranged at a first surface of a die pad. The die pad has a peripheral edge and a second surface opposite to the first surface that includes a first region and a second region surrounding the first region. The second region extends to the peripheral edge of the die pad from a border line at the first region and includes a recessed formation extending continuously along the border line. An insulating encapsulation is molded onto the die pad with the first region of the second surface left uncovered and the second region of the second surface of the die pad being covered by the insulating encapsulation that fills the recessed formation. The recessed formation has a variable recess depth between the border line and the peripheral edge of the die pad to provide an extended length delamination path from the border line to the semiconductor die.

Abstract: The HEMT device has a body including a heterostructure configured to generate a 2-dimensional charge-carrier gas; and a gate structure which extends on a top surface of the body and is biasable to electrically control the 2-dimensional charge-carrier gas. The gate structure has a channel modulating region of semiconductor material; a functional region of semiconductor material; and a gate contact region of conductive material. The functional region and the gate contact region extend on a top surface of the channel modulating region and the gate contact region is arranged laterally with respect to the functional region. The channel modulating region has a different conductivity type with respect to the functional region.

Abstract: Semiconductor chips are arranged on a first surface of a common electrically conductive substrate having an opposite second surface. The substrate includes adjacent substrate portions having mutually facing sides with sacrificial connecting bars extending between adjacent mutually facing sides. A solderable metallic layer is present on the second surface extending over the sacrificial connecting bars. The solderable metallic layer is selectively removed (by laser ablation or etching, for example) from at least part of the length the sacrificial connecting bars. The common electrically conductive substrate is then cut along the length of the elongate sacrificial connecting bars to provide singulated individual semiconductor devices. Undesired formation of electrically conductive filaments or flakes bridging parts of the substrate intended to be mutually isolated is countered.

Abstract: A delta-sigma modulator includes a loop filter circuit having a first input that receives an input signal and a second input that receives a feedback signal. The loop filter circuit generates a filtered signal. A quantizer circuit quantizes the integrated signal to generate an output signal. An anti-windup circuit detects instances where the integrated signal is outside an input signal input of the quantizer circuit and in response thereto generates a dead zone signal having a magnitude and sign corresponding to a difference between the filtered signal and the input signal range. The feedback signal is a sum of the output signal and the dead zone signal.

Abstract: A device includes a substrate and an interconnection network on the substrate. The interconnection network includes at least a first level, at least a second level and a third level. The first level includes one or more capacitors. The third level includes a metallic shield. The second level is positioned between the first level and the substrate. The capacitors of the first level are entirely separated from the substrate by the shield. The second level is located between the first and third levels.

Abstract: An electronic circuit includes image acquisition cells, wherein each cell has a photodetector coupled to a first node of the cell, and an amplifying transistor having a gate connected to the first node, a conduction node coupled to an output of the cell, and a node for controlling a back gate voltage. The amplifying transistor is configured so that its threshold voltage varies according to the back gate voltage. A control circuit adjusts a voltage applied to the control node of the back gate voltage of the amplifying transistor of one of the cells according to a comparison of the voltage present at the cell output and a reference voltage.

Abstract: Laser direct structure (LDS) material is molded onto a semiconductor chip arranged on a substrate. The LDS material has a first thickness between a front surface of the LDS material and the substrate. A portion of the LDS material is removed (with a blade, for instance) to form a cavity having an end wall between the front surface of the LDS material and an electrically conductive formation on the substrate. At the cavity, the LDS material has a second thick ness smaller than the first thickness. Laser beam energy is applied to the LDS material at the end wall of the cavity to structure therein one or more vias that extend between the end wall of the cavity and the electrically conductive formation. The semiconductor chip and the electrically conductive formation are electrically coupled with electrically conductive material grown in the one or more vias laser structured in the LDS material.

Abstract: A method performs a correction of an ionospheric error affecting pseudo-ranges measurements in a GNSS receiver receiving a plurality of satellite signals from a plurality of satellites of a constellation of satellites. The method is part of a navigation processing procedure performed at the GNSS receiver. The method utilizes pseudo range measurements previously calculated by the GNSS receiver, obtained from a plurality of carrier signals in the satellite signals. The method includes performing a correction procedure of the pseudo-range measurements, by calculating ionospheric error correction values for the pseudo-range measurements.

Abstract: A method for manufacturing a MEMS device includes forming a first solid body by forming, on a substrate, a layered structure having a thickness of a value comprised between 4 and 10 ?m, with the layered structure having a first surface that is uniformly flat or planar throughout the extension thereof that faces the substrate. The method further includes forming, on a second surface of the layered structure opposite to the first surface in a direction, multiple transducer devices. The method then proceeds with coupling the first solid body to a supporting structure, and completely removing the substrate to expose said uniformly flat or planar surface.

Abstract: A method and apparatus for aligning electrical contact formations, such as bumps or solder balls, at a first surface of a Wafer Level Chip Scale Package (WLCSP) semiconductor device with electrically conductive pins in an array of electrically conductive pins such as “pogo” pins is provided. The semiconductor device includes, opposite the first surface, a second surface protected by a protection layer. The method includes aligning the semiconductor device to a first alignment member by exposing the protected second surface of the semiconductor device to a chamfered surface in the first alignment member. A second alignment member is aligned to the array of electrically conductive pins. The electrical contact formations are aligned with respect to the array of electrically conductive pins as desired in response to the first and second alignment members being mutually aligned, in response to the semiconductor device being “landed” onto the array of electrically conductive pins.

Abstract: At least one embodiment of a method of manufacturing includes forming a first polycrystalline silicon carbide (SiC) substrate with a sintering process by sintering one or more powdered semiconductor materials. After the first polycrystalline SiC substrate is formed utilizing the sintering process, the first polycrystalline silicon carbide SiC substrate is utilized to form a second polycrystalline SiC substrate with a chemical vapor deposition (CVD) process. The second polycrystalline SiC substrate is formed on a surface of the first polycrystalline SiC substrate by depositing SiC on the surface of the first polycrystalline SiC substrate with the CVD process. As the first and second polycrystalline SiC substrates are made of the same or similar semiconductor material (e.g., SiC), a first coefficient of thermal expansion (CTE) for the first polycrystalline SiC substrate is the same or similar to the second CTE of the second polycrystalline SiC substrate.

Abstract: Various embodiments of wafers include a polycrystalline silicon carbide (SiC) layer or base substrate. The polycrystalline silicon carbide (SiC) layer may have a resistivity less than or equal to 2 mohm-cm (milliohm-centimeter) such that the polycrystalline silicon carbide layer is a low resistivity polycrystalline silicon carbide layer. The polycrystalline silicon carbide layer may have grains with a grain size less than or equal to 1 millimeter (mm), and may have a non-columnar structure. The polycrystalline silicon carbide layer may have a warpage less than or equal to 75 ?m (micrometers). A monocrystalline silicon carbide (SiC) layer may be coupled to the polycrystalline silicon carbide (SiC) layer by a bonding layer. The monocrystalline silicon carbide layer may be thinner than the polycrystalline silicon carbide layer.

Abstract: A polycrystalline silicon carbide (SiC) substrate with a density gradient between a first side of the polycrystalline SiC substrate and a second side of the polycrystalline SiC substrate opposite to the first side. A first density at the first side of the polycrystalline SiC substrate is less than a second density at the second side of the polycrystalline SiC substrate. The polycrystalline SiC substrate with the density gradient may be formed by forming a polycrystalline SiC base substrate with a sintering process followed by a post-sintering process. For example, the post sintering process may be at least one of the following of: applying a first temperature to the first side and a second temperature to the second side of the polycrystalline SiC substrate and performing a chemical vapor deposition (CVD) process to impregnate further silicon (Si) and carbon (C) atoms into the polycrystalline SiC base substrate.

Abstract: The present disclosure is directed to a voltage regulation circuit receiving as input an input voltage, in particular a DC voltage supply, and outputting a regulated voltage. The voltage regulation circuit includes a voltage reference circuit configured to supply a reference voltage which is independent, in particular with respect to temperature variations. The voltage regulation circuit includes a first circuit branch and a second circuit branch in parallel coupled between the input voltage and ground. The first branch includes a current generator including a first depletion MOSFET transistor, which gate source voltage is a PTAT (Proportional To Absolute Temperature) voltage, coupled between the input voltage and the voltage reference circuit.

Abstract: A coupling and chaining bridge is configured to receive an original data value via a first bus coupled to one of a system bus of an electronic device and a first peripheral circuit of the electronic device. The original data value is transmitted by the coupling and chaining bridge to a second bus of the electronic device coupled to the other of the system bus and the first peripheral circuit. The coupling and chaining bridge is further configured to intercept the original data value and transmit a copy of the original data value to a third bus of the device that is coupled to a second peripheral circuit of the device.

Abstract: A converter circuit is configured to convert a DC voltage into an AC voltage using a first thyristor and second thyristor in series in a first branch, a third thyristor and fourth thyristor in series in a second branch in an antiparallel configuration to the first branch, and a first transistor and second transistor in series in a third branch. When the AC voltage is equal to zero, and when the first thyristor is conductive and the first and second transistors are non-conductive, a first positive current is applied to the gate of the antiparallel third thyristor to control turn on and ensure that the current circulating in the first thyristor falls below the holding current.

Abstract: An insulating encapsulation encapsulates a semiconductor die having an integrated Hall current sensor configured to measure an electric current flowing adjacent an active surface of the semiconductor die. An electrically conductive trace is embedded in the insulating encapsulation. First electrically conductive formations extend through the insulating encapsulation towards opposed ends of the electrically conductive trace. The first electrically conductive formations are configured to cause an electrical current subject to measurement to flow in a current flow path through the electrically conductive trace. Second electrically conductive formations extend through the insulating encapsulation towards the active surface of the semiconductor die. The second electrically conductive formations are configured to activate the Hall current sensor integrated in the semiconductor die.

Abstract: The present disclosure relates to an avalanche photodiode pixel including: a transistor adapted to be controlled by an enable signal having a first state for controlling the enabling of the pixel and a second state for controlling the disabling of the pixel, the transistor being configured to couple an avalanche photodiode of the pixel to a node of application of a substrate voltage when the enable signal is in the first state; and an output circuit adapted to be controlled by the enable signal and configured to provide a pixel output signal when the enable signal is in the first state and to block the pixel output signal when the enable signal is in the second state.

Abstract: Microelectromechanical device comprising a supporting body, containing semiconductor material and a movable mass, constrained to the supporting body with a relative degree of freedom with respect to at least one motion direction, within a range of admissible positions. The device also comprises stopper elements, operable by the movable mass due to movements along the at least one motion direction and configured to apply stop forces to opposite sides of the movable mass, transversely to the at least one motion direction, when the movable mass reaches a respective endpoint of the range of admissible positions, so as to prevent the movable mass from exceeding the respective endpoint.