Abstract: A method for acquiring images using at least one CMOS-type sensor with four transistors including an acquisition node and a read node, where the read node can receive a compression signal, including a step of reading a reference state of the sensor; a reset step; an integration step, during which the sensor is exposed and during part of which the compression signal is applied to the read node; and a step of reading the data acquired during the integration step; the read node being, during the integration step, isolated from the acquisition node, except immediately before the application of the compression signal, at which time the acquisition node is connected to the read node long enough to enable a transfer of the charges present at the acquisition node to the read node.

Abstract: A method and system of controlling access to a programmable memory including: allowing code to be written to the programmable memory in a first access mode; preventing execution of the code stored in the programmable memory in the first access mode; verifying the integrity of the code stored in the programmable memory; if the integrity of the code stored in the programmable memory is verified, setting a second access mode, wherein in the second access mode, further code is prevented from being written to the programmable memory, and execution of the code stored in the programmable memory is allowed.

Abstract: A support wafer made of silicon wafer comprising, on a first surface a porous silicon layer having protrusions, porous silicon pillars extending from the porous silicon layer to the second surface of the wafer, in front of each protrusion. Layers constituting a fuel cell can be formed on the support wafer.

Abstract: A portable housing capable of being carried by a certain person includes a circuit. The circuit includes a memory for storing private data concerning that certain person, a circuit operable to effectuate storage of the private data in the memory in a secure manner, and a processing unit operable to control access to the memory for purposes of reading private data concerning the certain person from the memory and storing private data concerning the certain person to the memory. The conditions under which access to the memory for read and write operations with respect to the private data is permitted are governed by parameters that are specified by the certain person to whom the stored private data concerns. A biometric sensor may also be included to capture identification information useful in implementing the operations for controlling access to the memory.

Abstract: A reference signal generator circuit for an analog-to-digital converter, the circuit having a signal-generation stage to generate a first reference signal on a first reference terminal, and a filtering circuit arranged between the generator stage and the analog-to-digital converter to determine a filtering of disturbance present on the first reference signal and supply at output on a second reference terminal a second filtered reference signal, the filtering circuit having a switching circuit to connect the first reference terminal to the second reference terminal directly during startup of the reference signal generator circuit and then through the filtering circuit once the startup step is terminated.

Abstract: A protection layer is coated or otherwise formed over the interconnect structure. The interconnect structure includes a metal line (such as top and bottom metal layers connected by a metal via) and a low-K material. The protection layer includes a vertically aligned dielectric or other material dispersed with carbon nanotubes. The protection layer could include one or multiple layers of carbon nanotubes, and the carbon nanotubes could have any suitable dispersion, alignment, and pattern in each layer of the protection layer. Among other things, the carbon nanotubes help to reduce or prevent damage to the interconnect structure, such as by reducing or preventing the collapse of the low-K material or delamination between the metal line and the low-K material.

Abstract: A fail-safe level shifter switching with high speed and operational for a wide range of voltage supply includes a cascode module, and one or more speed enhancer modules. The cascode module receives one or more input logic signal for generating a plurality of output signals with a reduced switching time. The speed enhancer modules are coupled to the cascode module for facilitating faster charging and discharging of nodes of the cascode module and improving the robustness and operating voltage range of cascode module.

Abstract: An apparatus includes a plurality of call controllers that are capable of establishing a plurality of communication sessions over a packet network using a plurality of signaling protocols. The apparatus also includes an application controller that is capable of supporting one or more supplementary services during each of the communication sessions. As particular examples, the application controller and at least one of the call controllers are capable of at least one of: placing at least one of the communication sessions on hold so a user may initiate another of the communication sessions, placing at least one of the communication sessions on hold so the user may accept another of the communication sessions, and establishing a conference using at least two of the communication sessions. The communication sessions may use a common signaling protocol or different signaling protocols.

Abstract: A CMOS single photon avalanche diode (SPAD) design uses conventional, or at least known, CMOS processes to produce a device having a breakdown region in which the main p-n junction is formed of a deep n-well layer, and optionally on the other side, a p-add layer. The SPAD may also have a guard ring region which comprises the p-epi layer without any implant. The SPAD may have curved or circular perimeters. A CMOS chip comprises SPADs as described and other NMOS devices all sharing the same deep n-well.

Abstract: The present disclosure is directed to a semiconductor die having a chip outline boundary, a die seal, a row of input/output contact pads separated from the chip outline boundary by the die seal, a first row of solder bump connections positioned between the row of input/output contact pads and the die seal, and a second row of solder bump connections separated from the first row of solder bump connections by the row of input/output contact pads.

Abstract: A method is to de-correlate electric signals emitted by an IC Card during computations as well as sensitive data involved in such computations. The method includes executing functions introducing respective electric signals which do not involve the sensitive data. Each of the functions is triggered by a timer having a value which is different at each step of executing the functions.

Abstract: A system and method for optimizing power distribution in a closed system. In an electronic device, one may apply a plurality of driving algorithms for components that provide different variations functionality. Thus, each component may be operated according to one of several different algorithms depending on the level and manner of functionality needed. In this manner, the overall system may be optimized for any number of operating modes such that each component may conserve electrical power usage while still providing the needed functionality for specific components during each operating mode. Such an optimization assessment may be a function of an economic model applied to the system whereby functionality and components are assigned specific values and costs based on the required functionality for any given task. Thus, the amount of power available may be allocated in an efficient manner based on a cost-benefit analysis.

Abstract: Disclosed is a programmable pulse width discriminator circuit operable to receive a set of parameters from a user and indicate when an input signal satisfies conditions set by the user-defined parameters. The input signal is sampled by the pulse width discriminator circuit to detect a desired state of the input signal. The user may set the parameters such that the pulse width discriminator indicates the condition wherein the number of consecutive samples for which the input signal is the desired state is (i) greater than a first threshold value, (ii) less than a second threshold value, or (iii) between the first and second threshold values. In these embodiments, the user sets the first and second threshold values and selects which set of conditions are indicated by the output of the circuit.

Abstract: Disclosed is a deglitcher circuit having a programmable hysteresis. The deglitcher samples a received input signal, wherein the input signal may include one or more glitches. Responsive to a change in state of the sampled input signal, the deglitcher counts the number of samples of the changed state of the input signal. The count value increments with each sampled changed state, and decrements with each sampled original state of the input signal. When the count value reaches a threshold, the state of the output signal is changed. The output signal of the disclosed deglitcher circuit provides an accurate, glitch-free reconstruction of the sampled input signal. Additionally, the disclosed deglitcher circuit reduces the number of memory elements required for a given number of samples of the input signal, thereby allowing for a larger number of samples to be taken without necessarily having to increase the memory elements required by the deglitcher.

Abstract: A method manufactures a capacitor having polycrystalline dielectric layer between two metallic electrodes. The dielectric layer is formed by a polycrystalline growth of a dielectric metallic oxide on one of the metallic electrodes. At least one polycrystalline growth condition of the dielectric oxide is modified during the formation of the polycrystalline dielectric layer, which results in a variation of the polycrystalline properties of the dielectric oxide within the thickness of said layer.

Abstract: An assembly including: a first substrate having a first surface and housing a first electrical-interconnection element and a second electrical-interconnection element in a position corresponding to the first surface; a second substrate having a second surface, housing a third electrical-interconnection element and a fourth electrical-interconnection element in a position corresponding to the second surface, and provided with a dielectric layer extending on top of the third interconnection element; and a first bump and a second bump made of conductive material, extending between the first electrical-interconnection element and the third electrical-interconnection element and, respectively, between the second electrical-interconnection element and the fourth electrical-interconnection element, at least partially aligned to the respective electrical-interconnection elements, the first bump being ohmically coupled to the first interconnection element and capacitively coupled to the third interconnection element,

Abstract: Systems and methods are disclosed for determining the perceptibility of noise in a block of images and/or video. The systems and methods may compute a mask value for the block using a block masking generator. The mask value may indicate the perceptibility of noise in the block. The mask value may be computed using a normalized activity value and/or a texture value for the block. The normalized activity value may indicate the relative activity in the block as compared to the activity in the image and/or video. The texture value may indicate the strength and/or number of edges in the block.

Abstract: A method for protecting a thin-layer battery, including the steps of: periodically operating the battery at a forced discharge current, which is a function of temperature; and disconnecting the battery as soon as the voltage across it reaches a threshold, said threshold being greater than its critical voltage for a maximum discharge current under a maximum temperature.

Abstract: An electronic device is provided with: a first electronic circuit, integrated in a first die; a second electronic circuit, integrated in a second die; and a galvanic isolator element, designed to insulate galvanically, and to enable transfer of signals between, the first electronic circuit and the second electronic circuit. The galvanic isolator element has: a transformer substrate, distinct from the first die and from the second die; and a galvanic-insulation transformer formed by a first inductive element, integrated in the first die, and by a second inductive element, integrated in the transformer substrate and so arranged as to be magnetically coupled to the first inductive element.

Abstract: A system and method for optimal allocation of bandwidth in a multichannel transmission channel. In an embodiment, a system may allocate a specific amount of bandwidth in the transmission channel in order to maximize the value of the data that is transmitted on a per-channel basis. Typically, a transmission channel has enough bandwidth to accommodate the minimum bandwidth for all data across all channels. The excess bandwidth may be allocated in an optimal manner so as to provide additional bandwidth for the most valuable channels. The maximum allocation of bandwidth is a point in which allocating additional bandwidth to a channel does not yield any additional value. Such an allocation may be accomplished using an iterative analysis of the available bandwidth and a microeconomic-based analysis of the subjective value of each channel.