Abstract: An array of LED diodes includes N channels each having LEDs coupled in series with a switch. A current driver for the array includes a processing circuit configured to detect N currents flowing respectively through the N channels of the array. The detected currents are converted by a single analog to digital converter, one at a time, into a digital word. The circuit further includes N comparator devices configured to control the N switches as result of a comparison between the digital words and respective target digital words. A memory is provided for storing the digital words received from the analog to digital converter.

Abstract: A device includes an epitaxial region extending into a front surface of a chip. A portion of the chip adjacent the epitaxial region defines a collector. A gate is provided in a trench extending into the epitaxial region from the front surface. An emitter includes a body extending into the epitaxial region at a first side of the trench and a source extending into the body region from the front surface at the trench. A dummy emitter extends into the epitaxial region from the front surface at a second side of the trench opposite said first side. The dummy emitter lacks the source. The gate extends along a first wall of the trench facing the emitter region. A dummy gate is formed in the trench in a manner electrically isolated from the gate and extending along a second wall of the trench opposite said first wall.

Abstract: A current driver for a string of LEDs includes a first series connection of a first transistor and a first resistance and a second series connection of a second transistor and a second resistance. The first and second series connections are coupled in parallel between the string of LEDs and a voltage reference. An operational amplifier selectively drives the first and second transistors in response to a clock signal. A switch device driven by the clock signal alternately applies a reference voltage and a respective one of the voltages across the first and second resistances to inverting and non-inverting inputs of the operational amplifier in response to the clock signal. A storage circuit is coupled to the output of the operational amplifier to store the drive signals for the first and second transistors for application to the first and second transistors in the absence of output from the operational amplifier.

Abstract: A mirror micromechanical structure has a mobile mass carrying a mirror element. The mass is drivable in rotation for reflecting an incident light beam with a desired angular range. The mobile mass is suspended above a cavity obtained in a supporting body. The cavity is shaped so that the supporting body does not hinder the reflected light beam within the desired angular range. In particular, the cavity extends as far as a first side edge wall of the supporting body of the mirror micromechanical structure. The cavity is open towards, and in communication with, the outside of the mirror micromechanical structure at the first side edge wall.

Abstract: Embodiments reduce the complexity of speaker dependent speech recognition systems and methods by representing the code word (i.e., the word to be recognized) using a single Gaussian Mixture Model (GMM) which is adapted from a Universal Background Model (UBM). Only the parameters of the GMM need to be stored. Further reduction in computation is achieved by only checking the GMM component that is relevant to the keyword template. In this scheme, keyword template is represented by a sequence of the index of best performing component of the GMM of the keyword model. Only one template is saved by combining the registration template using Longest Common Sequence algorithm. The quality of the word model is continuously updated by performing expectation maximization iteration using the test word which is accepted as keyword model.

Abstract: An integrated circuit is produced on a bulk semiconductor substrate in a given CMOS technology and includes a semiconductor device for protection against electrostatic discharges. The semiconductor device has a doublet of floating-gate thyristors coupled in parallel and head-to-tail. Each thyristor has a pair of electrode regions. The two thyristors respectively have two separate gates and a common semiconductor gate region. The product of the current gains of the two transistors of each thyristor is greater than 1. Each electrode region of at least one of the thyristors has a dimension, measured perpendicularly to the spacing direction of the two electrodes of the corresponding pair, which is adjusted so as to impart to the thyristor an intrinsic triggering voltage less than the breakdown voltage of a transistor to be protected, and produced in the CMOS technology.

Abstract: A semiconductor device includes a capacitor formed in a semiconductor substrate of a first conductivity type. The capacitor includes: a heavily-doped layer of a second conductivity type placed over the substrate, a first insulating layer placed over the heavily-doped layer of the second conductivity type, and a first metal layer placed over the first insulating layer. The semiconductor device further includes comprises a second insulating layer deposited over the capacitor and at least one resistor formed over the second insulating layer. The resistor includes a layer of a resistive material region arranged between two regions of a second metal layer.

Abstract: A trimming circuit is configured to carry out a trimming operation on a device portion of an integrated circuit device. The trimming circuit includes: shunt fuses wherein each shunt fuse is coupled in parallel to a trimming resistance, further resistances wherein each further resistance is coupled in parallel to a respective shunt fuse. The circuit is configured to allow the flow of the trimming current when the respective shunt fuse is burnt during the trimming operation.

Abstract: A level shifter includes a first terminal configured to receive a first supply voltage, a second terminal configured to receive a second supply voltage, an input terminal configured to receive an input signal and an output terminal. The level shifter is configured to shift the input signal from the level of the first supply voltage to the level of the second supply voltage in outputting the output signal. The level shifter includes a storage circuit for storing the output signal value and configured, when the first supply voltage is no longer available, to force the output terminal to assume the last output voltage value stored by the storage circuit when the first supply voltage was available and before the first supply voltage was not available.

Abstract: An electronic semiconductor device comprising: a semiconductor body, having a first side and a second side opposite to one another and including a first structural region facing the second side, and a second structural region extending over the first structural region and facing the first side; a body region extending in the second structural region at the first side; a source region extending inside the body region; an LDD region facing the first side of the semiconductor body; and a gate electrode. The device comprises: a trench dielectric region extending through the second structural region a first trench conductive region immediately adjacent to the trench dielectric region; and a second trench conductive region in electrical contact with the body region and with the source region. An electrical contact at the second side of the semiconductor body is in electrical contact with the drain region via the first structural region.

Abstract: The invention relates to a method of protecting a security module (14) equipping a telecommunication device equipped with a near-field communication router (18), against an attempt to divert a channel for communication between a port of this security module and a port of the router, in which upon each request originating from the router and destined for the security module, the latter verifies the rights of access to the information that it contains as a function of the provenance of the request.

Abstract: An embodiment of a method for computing pyramids of input images (I) in a transformed domain, e.g., for search and retrieval purposes, includes:—arranging input images in blocks to produce input image blocks,—subjecting the input image blocks to block processing including: transform into a transformed domain, subjecting the image blocks transformed into a transformed domain to filtering, subjecting the image blocks transformed into a transformed domain and filtered to inverse transform implementing an inverse transform with respect to the previous transform into a transformed domain, thus producing a set of processed blocks. The set of processed blocks, which is recomposeable to an image pyramid, may be used, e.g., in detecting extrema points in images in the pyramid, extracting a patch of given size around the extrema points detected, and processing the patch to obtain local descriptors such as SIFT descriptors of a feature.

Abstract: The present disclosure describes a process strategy for forming bottom gate/bottom contact organic TFTs in CMOS technology by using a hybrid deposition/patterning regime. To this end, gate electrodes, gate dielectric materials and drain and source electrodes are formed on the basis of lithography processes, while the organic semiconductor materials are provided as the last layers by using a spatially selective printing process.

Abstract: A structure for starting a semiconductor component including a porous silicon layer in the upper surface of a semiconductor substrate. This porous silicon layer is contacted, on its upper surface side, by a metallization and, on its lower surface side, by a heavily-doped semiconductor region.

Abstract: A circuit for generating a D.C. signal for controlling an A.C. switch referenced to a first potential, from a high-frequency signal referenced to a second potential, including: a first capacitive element connecting a first input terminal, intended to receive the high-frequency signal, to the cathode of a rectifying element having its anode connected to a first output terminal intended to be connected to a control terminal of the switch; and a second capacitive element connecting a second input terminal, intended to be connected to the second reference potential, to a second output terminal intended to be connected to the first reference potential, a second rectifying element connecting the cathode of the first rectifying element to the second output terminal.

Abstract: A circuit includes a comparator having input terminals configured to be coupled across a drive transistor adapted to drive a phase of a motor. The comparator senses a drive current of the motor phase, said sensed drive current represented by a periodic signal whose period is indicative of motor speed. A motor speed calculation circuit receives the periodic signal and processes the periodic signal to determine a speed of the motor.

Abstract: In a memory device, a bitline write voltage is applied to a first bitline. A wordline voltage is applied to a first wordline for writing data to a first memory cell connected to the first wordline and the first bitline. The first bitline and the second bitline are electrically connected for charge sharing between the first bitline and the second bitline. A predetermined time after electrically connecting the first bitline and the second bitline, the first and the second bitline are electrically disconnected and the bitline write voltage is applied to the second bitline. The wordline voltage is applied to a second wordline for writing data to a second memory cell connected to the second wordline and the second bitline.

Abstract: The appearance of image details can be preserved and/or enhanced by applying contrast adaptive gain to the high spatial frequency component of the luminance information. The image details in bright and/or dark regions can be further boosted by applying a local mean adaptive gain. The contrast transfer mapping curve for luminance contrast enhancement can be re-scaled to account for the applied gain. The re-scaling may be performed from frame to frame of displayed video. The re-scaling may be temporally controlled for subsequent frames to make the re-scaling change gradually to prevent flickering.

Abstract: A node having a node input is configured to receive a plurality of transactions intended for a plurality of different targets. The node has multiple node outputs. At least one target is provided, that target including an input configured to receive a respective output of the node. The node is configured to direct transactions to the at least one target or an output (for passing to a different partition) depending on whether the transactions are intended for the target or a different target. This determination is made in response to a conversion operation which converts a target address of the transaction to an identification associated with the target or the output.

Abstract: An electrocatalytic polymer-based powder has particles of at least one electronically conductive polymer species in which particles are dispersed of at least one catalytic redox species, in which the particles of the polymer species and of the catalytic species are of nanometric dimension.