Abstract: A video decoder that separates and analyzes analog video signals includes a hue and saturation separator and a video signal determiner. The hue and saturation separator demodulates from a component video signal chroma signal, which includes a hue signal and a saturation signal. The video signal determiner determines at least one video signal characteristic of the component video signal dependent on the hue and saturation signal. The video signal determiner may include a mode determiner that determines the encoding standard of the video signal, and a color burst determiner that determines a location of a color burst signal with the video signal. The mode determiner may include a signal lock detector, a sequence matcher, and an encoding mode selector. The color burst determiner may include an absolute value determiner and a burst position determiner.

Abstract: A bandgap voltage reference circuit for generating a bandgap voltage reference. An embodiment comprises a current generator controlled by a first driving voltage for generating a first current depending on the driving voltage, and a first reference circuit element coupled to the controlled current generator for receiving the first current and generating a first reference voltage in response to the first current. The circuit further comprises a second reference circuit element for receiving a second current corresponding to the first current; said second reference circuit element is adapted to generate a second reference voltage in response to the second current. The circuit further comprises an operational amplifier having a first input coupled to the first circuit element and a second input coupled to the second reference circuit element. The circuit also comprises a control circuit comprising first capacitive element and second capacitive element.

Abstract: A method for producing an integrated device including a capacitor. The method includes the steps of providing a functional substrate including functional circuits of the integrated device, forming a first conductive layer including a first plate of the capacitor on the functional substrate, forming a layer of insulating material including a dielectric layer of the capacitor on a portion of the first conductive layer corresponding to the first plate, forming a second conductive layer including a second plate of the capacitor and functional connections to the functional circuits on a portion of the layer of insulating material corresponding to the dielectric layer, forming a protective layer of insulating material covering the second plate and the functional connections, forming a first contact for contacting the first plate, and forming a second contact and functional contacts for contacting the second plate and the functional connections, respectively, through the protective layer.

Abstract: An interface plate capable of being mounted between first and second surface-mounted electronic chips. The plate includes a plurality of first, second, and third through openings, the first openings being filled with a conductive material and being arranged to be in front of pads of the first and second chips during the assembly, the second openings being filled with a second material, the third openings being filled with a third material, the second and third materials forming two complementary components of a thermoelectric couple.

Abstract: A shallow trench is formed to extend into a handle substrate of a semiconductor-on-insulator (SOI) layer. A dielectric liner stack of a dielectric metal oxide layer and a silicon nitride layer is formed in the shallow trench, followed by deposition of a shallow trench isolation fill portion. The dielectric liner stack is removed from above a top surface of a top semiconductor portion, followed by removal of a silicon nitride pad layer and an upper vertical portion of the dielectric metal oxide layer. A divot laterally surrounding a stack of a top semiconductor portion and a buried insulator portion is filled with a silicon nitride portion. Gate structures and source/drain structures are subsequently formed. The silicon nitride portion or the dielectric metal oxide layer functions as a stopping layer during formation of source/drain contact via holes, thereby preventing electrical shorts between source/drain contact via structures and the handle substrate.

Abstract: A method for decoding a stream encoded using a scalable video coding and including a plurality of layers of frames divided into a plurality of blocks, decodes block-wise in parallel the layers of the stream. A target block in an enhancement layer is decoded as soon as the block data required for its decoding are available from the reference layer.

Abstract: A semiconductor device wherein a delay chain is integrated; the semiconductor device having a semiconductor layer. The delay chain includes a plurality of delay cells placed in the semiconductor layer and electrically connected to each other so as to form the delay chain. The semiconductor device includes a first and second metal lines respectively connected to a supply voltage and a reference voltage and placed in a longitudinal direction on a surface of the semiconductor layer; each delay cell of the plurality of cells is electrically connected with the first and second metal lines. Any delay cell and its successive or preceding delay cells of the delay chain are placed in a transversal direction with respect to the first or the second metal line.

Abstract: An integrated circuit includes an electrostatic discharge (ESD) detection circuit which detects an ESD event and generates an event signal. In response to that event signal, a control circuit controls the operation of a buffer circuit to function in an additional mode wherein the normal differential operation of the buffer circuit is disabled and the buffer circuit is instead configured to form a conduction path between supply rails to discharge the ESD event. Preferably, a plurality of buffer circuits are driven in parallel by the control circuit to function in the additional mode to form parallel discharge paths for the ESD event. Multiple ESD detection circuits may be provided, and any one of those detection circuits can trigger the control circuitry to place all of the buffer circuits in the additional mode.

Abstract: A thermoelectric generator including a membrane maintained by lateral ends and capable of taking a first shape when its temperature reaches a first threshold and a second shape when its temperature reaches a second threshold greater than the first threshold; at least one electrically conductive element attached to with the membrane and connecting the lateral ends of the membrane; and circuitry capable of generating, at the level of the membrane, a magnetic field orthogonal to the membrane displacement direction, the lateral ends of the membrane being connected to output terminals of the generator.

Abstract: A frequency-domain upmix process uses vector-based signal decomposition and methods for improving the selectivity of center channel extraction. The upmix processes described do not perform an explicit primary/ambient decomposition. This reduces the complexity and improves the quality of the center channel derivation. A method of upmixing a two-channel stereo signal to a three-channel signal is described. A left input vector and a right input vector are added to arrive at a sum magnitude. Similarly, the difference between the left input vector and the right input vector is determined to arrive at a difference magnitude. The difference between the sum magnitude and the difference magnitude is scaled to compute a center channel magnitude estimate, and this estimate is used to calculate a center output vector. A left output vector and a right output vector are computed. The method is completed by outputting the left output vector, the center output vector, and the right output vector.

Abstract: A system and method for determining the start position of a motor. According to an embodiment, a voltage pulse signal may be generated across a pair of windings in a motor. A current response signal will be generated and based upon the position of the motor, the response signal will be greater in one pulse signal polarity as opposed to an opposite pulse signal polarity. The response signal may be compared for s specific duration of time or until a specific integration threshold has been reached. Further, the response signal may be converted into a digital signal such that a sigma-delta circuit may smooth out glitches more easily. In this manner, the position of the motor may be determined to within 60 electrical degrees during a startup.

Abstract: A sink device having a display panel capable of performing a video frame self-refresh as directed by a source device is described. A source determines that a video frame will persist (i.e., remain the same). In this situation, the frame data does not need to be repeatedly transmitted over a main link between the source and sink devices. The main link can be turned off and transmission can cease for a certain time thereby reducing power usage by the devices or system as a whole. The source ensures that the last frame transmitted to the sink is correct by performing CRC checks and then instructs the sink, via certain bit settings in a video status indication symbol, to store the last transmitted frame in the sink's local buffer and use that frame to refresh the panel. The source can then disable the self-refresh when the frame changes.

Abstract: A wireless network access point generates a fast initial link setup (FILS) discovery frame for broadcast to one or more wireless stations. The wireless network access point supports many operating channels including a primary channel. The FILS discovery frame includes a data field populated with an identification of a channel number for that primary channel of the wireless network access point. The FILS discovery frame includes another data field populated with a primary channel operating class identification. The broadcast FILS discovery frame further includes data indicating whether indicating whether multiple BSSIDs are supported. An FD capability field of the FILS discovery frame includes sub-fields indicating one or more of operation channel width, PHY type of the wireless access point, number of spatial streams supported by the wireless access point and multiple BSSIDs support provided by the wireless access point.

Abstract: A printed circuit board including a first outer layer, a second outer layer and an integrated circuit mounted on the second outer layer. The integrated circuit has a single exposed pad electrically connected to a ground reference, a first supply pin electrically connected to a first power supply and a second supply pin electrically connected to a second power supply, wherein the first power supply is configured to generate a first supply current with frequency components higher than the frequency components of a second supply current generated by the second power supply.

Abstract: A relatively high-speed, high-efficiency CMOS two branch driver core that may operate under relatively low supply voltage may include thin oxide CMOS transistors configured to generate rail-to-rail output swings larger than twice a supply voltage and without exceeding safe operating area limits. Each of the two branches may include two stacked CMOS inverter pairs configured to drive a respective load capacitance coupled between respective CMOS inverter outputs, in phase opposition to the other branch. A pre-driver circuit input with a differential modulating signal may output two synchronous differential voltage drive signals of a swing of half of the supply voltage and DC-shifted by half of the supply voltage with respect to each other and that may be applied to the respective CMOS inverter inputs of the two branches.

Abstract: A duty cycle protection circuit including a first synchronous device adapted to receive a first clock signal on an input line and to generate a first clock transition of a second clock signal in response to a first clock transition of the first clock signal; and reset circuitry coupled to the input line and adapted to generate a second clock transition of the second clock signal by resetting the first synchronous device a time delay after the first clock transition of the first clock signal.

Abstract: A digital delay interpolator may include an array of multiplexers, each multiplexer configured to be input with first and second input voltages, one of the first and second input voltages being delayed in respect to the other, and receive a respective selection signal. The digital delay interpolator may include output lines respectively coupled to the array of multiplexers, and an output terminal configured to be coupled in common to the output lines. Each multiplexer may be configured to selectively output on the respective output line one of the first and the second input voltages based upon a logic value of the respective selection signal.

Abstract: Psychoacoustic bass audio signal enhancement can be accomplished using a monotonic, asymmetric polynomial distortion. A non-linear process applies a monotonic, asymmetric polynomial distortion function that has continuous first and second derivatives to generate even and odd harmonics of missing fundamental frequencies. This polynomial distortion produces the desired psychoacoustic effect with a fairly rapid roll-off so as to avoid unpleasant aliasing. Moreover, the lack of first-order discontinuities prevents clicks or glitches.

Abstract: An electronic device may include a bottom interconnect layer and an integrated circuit (IC) carried by the bottom interconnect layer. The electronic device may further include an encapsulation material on the bottom interconnect layer and laterally surrounding the IC. The electronic device may further include electrically conductive pillars on the bottom interconnect layer extending through the encapsulation material. At least one electrically conductive pillar and adjacent portions of encapsulation material may have a reduced height with respect to adjacent portions of the IC and the encapsulation material and may define at least one contact recess. The at least one contact recess may be spaced inwardly from a periphery of the encapsulation material.

Abstract: A multiband dynamics compressor implements a solution for minimizing unwanted changes to the long-term frequency response. The solution essentially proposes undoing the multiband compression in a controlled manner using much slower smoothing times. In this regard, the compensation provided acts more like an equalizer than a compressor. What is applied is a very slowly time-varying, frequency-dependent post-gain (make-up gain) that attempts to restore the smoothed long-term level of each compressor band.