Abstract: A system and a method to improve signal synchronization in a plurality of signal paths traversing multiple voltage domains. According to an embodiment of the present disclosure a memory arrangement is preferred for signal synchronization. All read/write and clocks signals and other control signals are driven to periphery supply (Vp) levels, except wordline (WL[i]) signals which are driven at core supply (Vc) level. By doing so, lower average and peak current consumption associated with core supply (Vc) is achieved with constant delays and maintaining required signal synchronization in the signal paths traversing multiple voltage domains.

Abstract: A surface mount package of a semiconductor device, has: an encapsulation, housing at least one die including semiconductor material; and electrical contact leads, protruding from the encapsulation to be electrically coupled to contact pads of a circuit board; the encapsulation has a main face designed to face a top surface of the circuit board, which is provided with coupling features designed for mechanical coupling to the circuit board to increase a resonant frequency of the mounted package. The coupling features envisage at least a first coupling recess defined within the encapsulation starting from the main face, designed to be engaged by a corresponding coupling element fixed to the circuit board, thereby restricting movements of the mounted package.

Abstract: A Class-G amplifier including a first and second driving transistor configured to receive an input voltage; a first supplying terminal connected to the first driving transistor to supply a first supplying voltage. The amplifier also comprises: a second supplying terminal connected to the second driving transistor to supply a second supplying voltage in absolute value higher than said first voltage; a first power transistor connected to the first driving transistor to form a first Sziklai pair structured to be activated by a first input voltage lower in absolute value than the first supplying voltage; a second power transistor connected to the second driving transistor to form a second Sziklai pair structured to be activated by an input signal comprised between the first supplying voltage and the second supplying voltage.

Abstract: Enhanced low power medium access (LPMA) processes involve the enhanced LPMA STA indicating low power capabilities during association and being allocated an AID. The AID(s) for one or a group of enhanced LPMA STA(s) are included in one TIM sent during a different BEACON interval than the AID(s) for another or another group of enhanced LPMA STA(s). In addition, or alternatively, the AID(s) for enhanced LPMA STA(s) are located at an edge of the AID set within a TIM, a portion of the TIM that may be easily truncated and therefore not sent. The enhanced LPMA STAs and associated access point negotiate unique offset and sleepinterval periods for polling or data uplink by the enhanced LPMA STAs.

Abstract: A passive filter may include at least one elliptical filter unit and at least one asymmetric rejection filter unit coupled in series with the elliptical filter unit. The at least one asymmetric rejection filter unit may have a frequency response curve that includes a dip with different attenuations on either side, and an overshoot upon exiting the dip at the side with the lower attenuation.

Abstract: An integrated detection structure has a first inertial mass and a second inertial mass, each of which is elastically anchored to a substrate and has a linear movement along a first horizontal axis, a first detection movement of rotation about a first axis of rotation parallel to a second horizontal axis and a second detection movement of translation along the second horizontal axis; driving electrodes cause linear movement of the inertial masses, in opposite directions of the first horizontal axis; a pair of flexural resonator elements and a pair of torsional resonator elements are elastically coupled to the inertial masses, the torsional resonator elements having a resonant movement of rotation about a second axis of rotation and a third axis of rotation, parallel to one another and to the first axis of rotation.

Abstract: A readout device for a capacitive sense matrix includes a computer readable storage medium configured to store capacitance data. The capacitance data represents capacitance values of the capacitive sense matrix. The readout device also includes a readout circuit configured to receive a signal from the capacitive sense matrix, the readout circuit being configured based upon the capacitance data. Also described are a readout method and a method of compensating for variations in capacitance.

Abstract: A system includes a processor and a plurality of circuits connected through an interconnection network, wherein associated to each circuit is a respective communication interface configured for exchanging data between the respective circuit and the interconnection network. In particular, a debug unit is associated with each communication interface. Each debug unit is configurable as a data-insertion point, wherein the debug unit transmits data by means of the respective communication interface to the interconnection network, or each debug unit is configurable as a data-reception point, wherein the debug unit receives data by means of the respective communication interface from the interconnection network.

Abstract: A method for simultaneous playback of audio tracks from digital transceiver devices, which are adapted to define a communication network. The digital devices store audio tracks to be played. One of the digital devices is actuated as a Master device (M) and the remaining N digital devices as Slave devices. The master device generates a pilot signal by selecting a pilot audio track to be played from among stored audio tracks and by adding a synchronization frequency (fS) to the pilot audio track, having an assigned value that falls out of the sound wave frequency range. The Slave devices receive a pilot portion of the pilot signal and extract the synchronization frequency and the received part of the pilot audio track. The slave devices use the pilot to identify a stored track to be played using the synchronization frequency as a sampling frequency.

Abstract: A semiconductor device may include at least one pad adjacent a top surface of the device, and a metal crack stop structure below the at least one pad. The metal crack structure may have an inner envelope and an outer envelope, and may be configured to be vertically aligned with the at least one pad so that an edge of the at least one pad is between the inner and outer envelopes.

Abstract: A method is provided for managing the operation of a circuit operating in a slave mode. The circuit is connected to a bus having at least two of wires and a priority logic level. The slave circuit imposes the priority logic level on a first wire of the bus. While imposing, the slave circuit detects a possible conflict on the first wire resulting from a forcing, external to the slave circuit, of the first wire to another logic level. Upon detecting a conflict, the slave circuit is placed in a state stopping the sending by the circuit of any data over the bus while leaving the circuit listening to the bus.

Abstract: A touch screen system is configured to sense a proximate or actual touch made to a touch screen panel. In response thereto, an RF transmitter is actuated to emit RF energy. A stylus receives the emitted RF energy and includes an RF energy harvesting circuit that powers an enable circuit. The enable circuit generates an enable signal. The stylus responds to the enable signal by performing a sensing operation. The information collected in the sensing operation is then communicated over an RF communications link back to the touch screen system. The sensing operation preferably is a pressure sensing operation for detecting an applied pressure at an end of the stylus resulting from contact with the touch screen panel.

Abstract: A comparator circuit includes an input differential amplifier circuit generating an output signal and an inverting output circuit generating a complemented output signal. The differential amplifier circuit is formed of a differential pair of input transistors and a pair of diode connected load transistors. The comparator circuit is integrated in a silicon on insulator type structure. A hysteresis-creating circuit is formed by coupling one or more of the output signal and complemented output signal to a substrate region (in the silicon on insulator type structure) associated with one or more of the differential pair of input transistors and pair of diode connected load transistors. The differential amplifier circuit may further include auxiliary transistors coupled to the diode connected load transistors and the hysteresis-creating circuit may further couple one or more of the output signal and complemented output signal to the substrate region associated with the auxiliary transistor.

Abstract: An imaging device may include a housing, an image sensor IC in the housing, a lens adjacent the image sensor IC, and a cap over the lens and having an adhesive filling opening therein. The cap, the housing, and the lens may define an adhesive receiving cavity therein and in communication with the adhesive filling opening. The imaging device may also include adhesive material within the adhesive receiving cavity touching the cap, the housing, and the lens.

Abstract: A display screen is configured to display information with a selectable one of many information display orientations. A touch screen panel of a touch screen system is positioned to overlie the display screen. The touch screen system operates to make a proximate touch detection, for example by a body part or stylus. A controller receives the proximate touch information from the capacitive touch screen system and interprets the proximate touch information to determine an indication from a user of a selection of an information display orientation for the display screen. The controller then controls the display screen to present information in accordance with the user selected information display orientation. The user selected information display orientation via the proximate touch detection will over-ride any other selected information display orientation such as a selection made in response to an orientation identified by an accelerometer or other gravity influenced sensor.

Abstract: An LIN transmitter includes a current mirror coupled to a transmit output node and a control circuit coupled to a transmit input node for controlling the current mirror with various load current control signals.

Abstract: According to one embodiment of the invention, the gate contact is formed by a selective deposition on the gate electrode. One acceptable technique for the selective deposition is by plating. Plating is one process by which a metal structure, such as a gate contact, may be formed directly on the gate electrode. The plating is carried out by immersing the semiconductor die in a plating solution with the gate electrode exposed. The gate contact is plated onto the gate electrode and thus is ensured of being fully aligned exactly to the gate electrode. After this, the appropriate dielectric layers are formed adjacent the gate contact and over the source and drain to ensure that the gate electrode is electrically isolated from other components of the transistor.

Abstract: A method for transmitting data between a first and a second point comprises the steps of transmitting data, from the first to the second point, together with a signature comprising bits of a first authentication code, and transmitting an acknowledgement, from the second to the first point. The length of the first authentication code is greater than the length of the signature and the first authentication code comprises hidden authentication bits. The acknowledgement is produced by using hidden authentication bits of a second authentication code presumed to be identical to the first, produced at the second point.

Abstract: A photosite may include, in a semi-conductor substrate, a photodiode pinched in the direction of the depth of the substrate including a charge storage zone, and a charge transfer transistor to transfer the stored charge. The charge storage zone may include a pinching in a first direction passing through the charge transfer transistor defining a constriction zone adjacent to the charge transfer transistor.

Abstract: A system and method for utilizing multiple configurable lanes for clock and data transfer in source synchronous systems that may utilize a clock signal from another source for interpreting data received from the source. In an embodiment, a system may include a transmitter configured to transmit at least one clock signal and at least one data signal to a receiver device. The receiver device may have at least one clock lane and at least one data lane for receiving signals from the transmitter device. The clock lane(s) and data lane(s) can be arranged in any order as per requirement of system design. In the receiver, after manufacture, each data lane may be configured to be clocked by any clock lane.