Patents Assigned to STMicroelectronics
  • Patent number: 8688995
    Abstract: The invention concerns a method of detecting a fault attack including providing a plurality of blinding values; generating a first set of data elements including a first group of data elements and at least one additional data element generated by performing the exclusive OR between at least one data element in the first group and at least one of the blinding values; generating a second set of data elements corresponding to the exclusive OR between each data element of the first set and a selected one of the plurality of blinding values; generating a first signature by performing a commutative operation between each of the data elements of the first set; generating a second signature by performing the commutative operation between each of the data elements of the second set; and comparing the first and second signatures to detect a fault attack.
    Type: Grant
    Filed: November 10, 2010
    Date of Patent: April 1, 2014
    Assignee: STMicroelectronics (Rousset) SAS
    Inventor: Yannick Teglia
  • Patent number: 8687897
    Abstract: A method for detecting orientation of the contours in an image, performs an initial transformation of the image using a non-decimated multi-resolution transform, segments the image into a plurality of blocks, determines the optimal resolution for each block, and detects the predominant direction of contour for each of the blocks.
    Type: Grant
    Filed: January 3, 2011
    Date of Patent: April 1, 2014
    Assignee: STMicroelectronics (Grenoble 2) SAS
    Inventors: Eric Van Reeth, Pascal Bertolino, Nicolas Marina
  • Patent number: 8687563
    Abstract: In order to satisfy the conflicting requirements for spectrum sensing and QoS of data transmission, it is highly desirable for a cognitive radio system, e.g. IEEE 802.22 WRAN, to perform spectrum sensing and data transmission simultaneously. Embodiments of the invention address critical issues of self-interference generated from a transmission unit to the co-located sensing unit when the simultaneous sensing and data transmission technique is applied. A number of interference mitigation techniques are described and analysis are given.
    Type: Grant
    Filed: December 28, 2007
    Date of Patent: April 1, 2014
    Assignee: STMicroelectronics, Inc.
    Inventor: Wendong Hu
  • Patent number: 8688872
    Abstract: A method for managing a queue, such as for example a FIFO queue, and executing a look-ahead function on the data contained in the queue includes associating to the data in the queue respective state variables (C1, C2, . . . CK), the value of each of which represents the number of times a datum is present in the queue. The look-ahead function is then executed on the respective state variables, preferentially using a number of state variables (C1, C2, . . . CK) equal to the number of different values that may be assumed by the data in the queue. The look-ahead function can involve identification of the presence of a given datum in the queue and is, in that case, executed by verifying whether among the state variables (C1, C2, . . . CK) there exists a corresponding state variable with non-nil value.
    Type: Grant
    Filed: November 22, 2010
    Date of Patent: April 1, 2014
    Assignee: STMicroelectronics S.r.l.
    Inventors: Daniele Mangano, Giovanni Strano, Salvatore Pisasale
  • Patent number: 8687329
    Abstract: A structure for protecting a circuit connected to first and second rails of a telephone connection against overvoltages, including: first and second diodes in anti-series between the first and second rails; a first capacitor in parallel with a first resistor between a first node common to the first and second diodes and a low voltage reference node; and a protection element capable of removing fast overvoltages between any of the rails and the low reference voltage node when these overvoltages exceed a first threshold associated with the voltage of the first node.
    Type: Grant
    Filed: June 6, 2011
    Date of Patent: April 1, 2014
    Assignee: STMicroelectronics (Tours) SAS
    Inventors: Cédric Appere, André Bremond, Christian Ballon
  • Patent number: 8686515
    Abstract: A mesa-type bidirectional vertical power component, including a substrate of a first conductivity type; a layer of the second conductivity type on each side of the substrate; first regions of the first conductivity type in each of the layers of the second conductivity type; and, at the periphery of each of its surfaces, two successive grooves, the internal groove crossing the layers of the second conductivity type, second doped regions of the first conductivity type being formed under the surface of the external grooves and having the same doping profile as the first regions.
    Type: Grant
    Filed: December 21, 2011
    Date of Patent: April 1, 2014
    Assignee: STMicroelectronics (Tours) SAS
    Inventors: Yannick Hague, Samuel Menard
  • Publication number: 20140083206
    Abstract: A planar electric circuit board may include a planar support of a foldable material defining a base surface and wings coupled to the base surface along respective folding lines so that the wings, when folded along the folding lines, are erected with respect to the base surface and remain in that position. An auxiliary circuit is on the planar support and may include pairs of capacitive coupling plates defined on the wings and on the base surface, and electric communication lines coupled to corresponding ones of the pairs of capacitive coupling plates.
    Type: Application
    Filed: September 16, 2013
    Publication date: March 27, 2014
    Applicant: STMICROELECTRONICS S.R.L.
    Inventors: Alberto PAGANI, Federico Giovanni ZIGLIOLI
  • Publication number: 20140084519
    Abstract: The present disclosure relates to mold components and imprint lithography techniques applied on the basis of organic mold materials in order to form polymer microstructure elements. It has been recognized that adapting surface characteristics of at least one mold component may significantly enhance performance of the lithography process, in particular with respect to suppressing residual polymer material, which in conventional strategies may have to be removed on the basis of an additional etch process.
    Type: Application
    Filed: September 18, 2013
    Publication date: March 27, 2014
    Applicants: Fondazione Istituto Italiano di Tecnologia, STMicroelectronics S.r.l.
    Inventors: Fabrizio Porro, Antonio Scognamiglio, Raffaele Vecchione, Valeria Casuscelli, Andrea Di Matteo, Luigi Giuseppe Occhipinti, Paolo Netti
  • Publication number: 20140087524
    Abstract: The substrate successively includes a support substrate, an electrically insulating layer, a semiconductor material layer, and a gate pattern. The semiconductor material layer and gate pattern are covered by a covering layer. A first doping impurity is implanted in the semiconductor material layer through the covering layer so as to place the thickness of maximum concentration of the first doping impurity in the first layer. The covering layer is partly eliminated so as to form lateral spacers leaving source/drain electrodes free.
    Type: Application
    Filed: June 9, 2011
    Publication date: March 27, 2014
    Applicants: STMICROELECTRONICS, INC., COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Nicolas Posseme, Laurent Grenouillet, Yannick Le Tiec, Nicolas Loubet, Maud Vinet
  • Publication number: 20140084909
    Abstract: A building structure includes a block of building material and a magnetic circuit buried in the block of building material. The structure also includes a plurality of sensing devices buried in the block of building material. Each sensing device may include a contactless power supplying circuit magnetically coupled with the magnetic circuit to generate a supply voltage when the magnetic circuit is subject to a variable magnetic field.
    Type: Application
    Filed: September 16, 2013
    Publication date: March 27, 2014
    Applicant: STMICROELECTRONICS S.R.L.
    Inventor: Alberto PAGANI
  • Publication number: 20140084876
    Abstract: An energy-scavenging interface includes first and second switches connected in series between an input and reference, and third and fourth switches connected in series between the input and an output. A control circuit closes the first and second switches and opens the third switch for a first time interval to store charge in a storage element. A scaled copy of a peak value of the charging current is obtained. The control circuit then opens the first switch and closes the third and fourth switches to generate an output signal as long as the value in current of the output signal is higher than the value of said scaled copy of the peak value.
    Type: Application
    Filed: September 25, 2013
    Publication date: March 27, 2014
    Applicant: STMicroelectronics S.r.I.
    Inventors: Stefano Ramorini, Alessandro Gasparini, Alberto Cattani
  • Publication number: 20140084900
    Abstract: An energy-scavenging interface receives an input signal from a transducer and supplies an output signal to a load. A switch is connected between the transducer and a reference node, and a diode is connected between the transducer and the load. A control circuit closes the switch for a time interval to permit energy storage in the transducer. A scale copy of a peak value of stored electric current is obtained. The switch is opened when the time interval elapses and the stored energy exceeds a threshold. The stored energy is then released to supply the load through the diode. The switch remains open as long as the value of current in the output signal exceeds the value of the scaled copy of the peak value.
    Type: Application
    Filed: September 25, 2013
    Publication date: March 27, 2014
    Applicant: STMicroelectronics S.r.I.
    Inventors: Stefano Ramorini, Alessandro Gasparini, Alberto Cattani
  • Publication number: 20140084372
    Abstract: A shallow trench is formed to extend into a handle substrate of a semiconductor-on-insulator (SOI) layer. A dielectric liner stack of a dielectric metal oxide layer and a silicon nitride layer is formed in the shallow trench, followed by deposition of a shallow trench isolation fill portion. The dielectric liner stack is removed from above a top surface of a top semiconductor portion, followed by removal of a silicon nitride pad layer and an upper vertical portion of the dielectric metal oxide layer. A divot laterally surrounding a stack of a top semiconductor portion and a buried insulator portion is filled with a silicon nitride portion. Gate structures and source/drain structures are subsequently formed. The silicon nitride portion or the dielectric metal oxide layer functions as a stopping layer during formation of source/drain contact via holes, thereby preventing electrical shorts between source/drain contact via structures and the handle substrate.
    Type: Application
    Filed: December 4, 2013
    Publication date: March 27, 2014
    Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION, COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, STMICROELECTRONICS, INC.
    Inventors: Bruce B. Doris, Shom Ponoth, Prasanna Khare, Qing Liu, Nicolas Loubet, Maud Vinet
  • Publication number: 20140087539
    Abstract: A process for manufacturing a semiconductor device, wherein a semiconductor layer is formed on a body of semiconductor material; a first mask is formed on the semiconductor layer; a first conductive region is implanted in the body using the first mask; a second mask is formed laterally and complementarily to the first mask, at least in a projection in a plane parallel to the surface of the body; a second conductive region is implanted in the body using the second mask, in an adjacent and complementary position to the first conductive region; spacers are formed on the sides of the second mask region, to form a third mask aligned to the second mask; and, using the third mask, portions of the semiconductor layer are removed to form a gate region.
    Type: Application
    Filed: September 19, 2013
    Publication date: March 27, 2014
    Applicant: STMicroelectronics S.r.I.
    Inventor: Francesco Lizio
  • Publication number: 20140083557
    Abstract: A photoresist delivery system includes a photoresist pump, a photoresist reservoir coupled to the photoresist pump, and a photoresist container. A control valve is between the photoresist reservoir and the photoresist container and is movable from a closed position to an open position upon engagement of the photoresist container with the photoresist reservoir to replenish photoresist therein.
    Type: Application
    Filed: September 24, 2012
    Publication date: March 27, 2014
    Applicant: STMicroelectronics Pte Ltd.
    Inventors: Gino GEORGE, KeenYip Koh, CheeChiang LEE, Ditto ADNAN
  • Publication number: 20140084397
    Abstract: A wafer-level package for a MEMS integrated device, envisages: a first body integrating a micromechanical structure; a second body having an active region integrating an electronic circuit, coupled to the micromechanical structure; and a third body defining a covering structure for the first body. The second body defines a base portion of the package and has an inner surface coupled to which is the first body, and an outer surface provided on which are electrical contacts towards the electronic circuit; a routing layer has an inner surface set in contact with the outer surface of the second body and an outer surface that carries electrical contact elements towards the external environment. The third body defines a covering portion for covering the package and is directly coupled to the second body for closing a housing space for the first body.
    Type: Application
    Filed: September 18, 2013
    Publication date: March 27, 2014
    Applicant: STMicroelectronics S.r.I.
    Inventor: Federico Giovanni Ziglioli
  • Publication number: 20140089885
    Abstract: A first assembly of critical cells is to be monitored. An equivalent capacitance of output cells coupled to the critical path is determined. Logic level inputs of the critical cells for signal propagation are also determined. A second assembly of control logic cells is provided which copies the first assembly in terms of number of cells, type of cells and cell connection such that each of the control cells is a homolog of a corresponding critical cell. Charge cells are provided at the outputs of the control cells having an equivalent capacitance in accordance with the determined capacitance of the output cells. For each control cell, logic levels are asserted in accordance with the determined configuration of the critical path. A signal generator applies a signal the input of the second assembly and a signal receiver is coupled to the output of the second assembly.
    Type: Application
    Filed: September 16, 2013
    Publication date: March 27, 2014
    Applicant: STMICROELECTRONICS SA
    Inventors: Julien Le Coz, Sylvain Engels, Alain Tournier
  • Publication number: 20140085260
    Abstract: An embodiment of a method for processing finger-detection data produced by a touch screen includes: computing the area of the finger-data map and extracting the main axes from the finger-data map, computing the lengths and orientations of the main axes, determining from the main axes a major axis having a major-axis orientation, computing a geometrical center and a center of mass of the finger-data map, computing an eccentricity of the finger-data map as a function of the lengths of the main axes outputting the major-axis orientation as indicative of the finger-orientation direction in the plane of the screen, outputting the mutual position of the geometrical center and the center of mass of the finger-data map as indicative of finger-pointing direction along the finger-orientation direction in the plane of the screen, and outputting a combination of the eccentricity and the area of the finger data map as indicative of finger orientation with respect to the plane of the screen.
    Type: Application
    Filed: September 25, 2013
    Publication date: March 27, 2014
    Applicant: STMicroelectronics S.r.L.
    Inventors: Nunziata Ivana GUARNERI, Alessandro CAPRA
  • Publication number: 20140084465
    Abstract: A plurality of metal tracks are formed in an integrated circuit die in three metal layers stacked within the die. A protective dielectric layer is formed around metal tracks of an intermediate metal layer. The protective dielectric layer acts as a hard mask to define contact vias between metal tracks in the metal layers above and below the intermediate metal layer.
    Type: Application
    Filed: September 27, 2012
    Publication date: March 27, 2014
    Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION, STMICROELECTRONICS, INC.
    Inventors: John H. Zhang, Lawrence A. Clevenger, Carl Radens, Yiheng Xu
  • Publication number: 20140084308
    Abstract: A sensor package is provided having a light sensitive component and a light emitting component attached to a same substrate. Light from the light emitting component is emitted from the package through a first opening and reflected back into the package to the light sensitive component through a second opening in the package. A glass attachment is placed between the light emitting component and the light sensitive component. A portion of the glass is removed and filled with an opaque substance to prevent light travelling between the light emitting component and the light sensitive component in the package.
    Type: Application
    Filed: September 27, 2012
    Publication date: March 27, 2014
    Applicant: STMicroelectronics Pte Ltd.
    Inventors: Wing Shenq Wong, Hk Looi