Abstract: The present disclosure relates to microstructure devices, in which a conductive pattern is formed on the basis of a conductive polymer material. In order to avoid the deposition and processing of the sacrificial materials and reduce a negative influence of the lithography process on sensitive conductive polymer materials a one-layer patterning sequence is proposed, in which a trench pattern is formed in a dielectric material that is subsequently filled with the conductive polymer material.

Abstract: A step-counter device detects and counts user steps. The device includes a transducer configured to generate an electrical transduction signal in response to user stepping. An energy-scavenging system is coupled to the transducer to generate a power supply voltage in response to the electrical transduction signal. A processing unit is powered by the power supply voltage. The processing unit is further configured to sense the electrical transduction signal and determine whether a user step has occurred and in response to that determination increment a step counter.

Abstract: A multi-layer capacitor of staggered construction is formed of one or more layers having tapered sidewall(s). The edge(s) of the capacitor film(s) can be etched to have a gentle slope, which can improve adhesion of the overlying layers and provide more uniform film thickness. The multi-layer capacitor can be used in various applications such as filtering and decoupling.

Abstract: The methods and systems of this invention allow for independent adaptive control of ringing and overshoot effects in 2-dimensional array interpolation processes, including in image and video rescaling and analysis. The methods and systems can use either a column-wise or a row-wise interpolation, or a combination thereof. Each uses a respective preliminary interpolation of data, followed by ringing and/or overshoot control. Controllable parameters allow variability in the amount of ringing and/or overshoot retained in the interpolated data. The ringing and overshoot controls apply a local analysis of the data to adjust the preliminary interpolation results. The methods may be repeated iteratively, for example, to obtain a desired rescaling of an image data array.

Abstract: A memory cell is formed by storage latch having a true node and a complement node. The cell includes a write port operable in response to a write signal on a write word line to write data from write bit lines into the latch, and a separate read port operable in response to a read signal on a read word line to read data from the latch to a read bit line. The circuitry of the memory cell is configured to address voltage bounce at the complement node during reading of the memory (where the voltage bounce arises from a simultaneous write to another memory cell in a same row).

Abstract: A method for manufacturing a micro-electro-mechanical device, which has supporting parts and operative parts, includes providing a first semiconductor wafer, having a first layer of semiconductor material and a second layer of semiconductor material arranged on top of the first layer, forming first supporting parts and first operative parts of the device in the second layer, forming temporary anchors in the first layer, and bonding the first wafer to a second wafer, with the second layer facing the second wafer. After bonding the first wafer and the second wafer together, second supporting parts and second operative parts of said device are formed in the first layer. The temporary anchors are removed from the first layer to free the operative parts formed therein.

Abstract: A process for fabricating a transistor may include forming source and drain regions in a substrate, and forming a floating gate having electrically conductive nanoparticles able to accumulate electrical charge. The process may include deoxidizing part of the floating gate located on the source side, and oxidizing the space resulting from the prior deoxidation so as to form an insulating layer on the source side.

Abstract: An electronic system, an integrated circuit and a method for display are disclosed. The electronic system contains a first device, a memory and a video/audio compression/decompression device such as a decoder/encoder. The electronic system is configured to allow the first device and the video/audio compression/decompression device to share the memory. The electronic system may be included in a computer in which case the memory is a main memory. Memory access is accomplished by one or more memory interfaces, direct coupling of the memory to a bus, or direct coupling of the first device and decoder/encoder to a bus. An arbiter selectively provides access for the first device and/or the decoder/encoder to the memory based on priority. The arbiter may be monolithically integrated into a memory interface. The decoder may be a video decoder configured to comply with the MPEG-2 standard. The memory may store predicted images obtained from a preceding image.

Abstract: In a method for recovery of a dock from a received digital data stream and an apparatus for recovering a clock from a received digital data stream, phase-shifted dock signals are generated from a receiver's dock. After selecting one of the phase-shifted clock signals, two other phase-shifted clock signals are determined. Depending on sample values taken at rising/falling edges of the three selected phase-shifted clock signals, counter values are increased and compared. The selection of phase-shifted clock signals and the steps of sampling the input digital data stream, comparing the values and increasing counter values, if required, are repeatedly performed until the comparison result of the counter values indicates that one of the latter determined phase-shifted clock signals strobes the received digital data stream in the center of a bit period.

Abstract: A method for encoding video signals subjects the signals to unbalanced multiple description coding. The unbalanced multiple description coding codes a video signal in a first high resolution packet and a second low resolution packet and represents, respectively a first high resolution description and a second low resolution description. The unbalanced multiple description coding step includes using different intra refresh periods for the first and second high resolution descriptions, with an intra refresh period for the second low resolution description shorter than the intra refresh period of the first high resolution description.

Abstract: A method is provided for fabricating a vertical insulated gate transistor. A horizontal isolation region is formed in a substrate to separate and electrically isolate upper and lower portions of the substrate. A vertical semiconductor pillar with one or more flanks and a cavity is formed so as to rest on the upper portion, and a dielectrically isolated gate is formed so as to include an internal portion within the cavity and an external portion resting on the flanks and on the upper portion. One or more internal walls of the cavity are coated with an isolating layer and the cavity is filled with a gate material so as to form the internal portion of the gate within the cavity and the external portion of the gate that rests on the flanks, and to form two connecting semiconductor regions extending between source and drain regions of the transistor.

Abstract: A macro-block (MB) quantization reactivity compensation method for a video encoder is provided. The method calculates a reference picture quantization value based on a calculated picture complexity. This predicted reference quantization is combined with the bits-used reactive MB reference quantization value to determine the final MB reference quantization value. This MB reference quantization value is also made adaptive to the VBV buffer fullness, as well as to the predicted change of the current picture complexity. A video encoder and an article of manufacture that comprises computer readable program code for execution of the method are also provided.

Abstract: A semiconductor device having a gate positioned in a recess between the source region and a drain region that are adjacent either side of the gate electrode. A channel region is below a majority of the source region as well as a majority of the drain region and the entire gate electrode.

Abstract: Imaging device comprising at least one photosite comprising a charge storage semiconductor zone, a charge collection semiconductor zone and transfer means designed to permit charge transfer between the charge storage zone and the charge collection zone, characterized in that the charge storage semiconductor zone comprises a lower semiconductor zone and a conduction channel buried beneath the upper surface of the photosite and connecting said lower semiconductor zone to the charge collection zone.

Abstract: An apparatus and method for coding block boundary detection using interpolated autocorrelation is disclosed. Input video frames are processed to obtain a binary map of possible block boundary pixels including original and rescaled block boundaries. The boundary pixel map is converted to a boundary histogram. Then interpolated autocorrelation is applied to the boundary histogram to detect the block size and block size offset. The interpolated autocorrelation handles both integer sizes and non-integer sizes. A confidence measure is also determined that reflects the accuracy of the detection result. The output for the current video frame is also post processed with information from previous frames to provide better temporal stability.

Abstract: A MEMS microbalance that includes a substrate made of semiconductor material with a cavity, and a resonator, which is suspended above the cavity of the substrate and is formed by a mobile body, by at least one first arm connected between the substrate and the mobile body, which has a first thickness and which enables oscillations of the mobile body with respect to the substrate, by an actuation transducer connected to the mobile body for generating the oscillations at a resonance frequency, and by a detection transducer for detecting a variation of the resonance frequency, wherein the mobile body possesses at least one thin portion having a second thickness smaller than the first thickness of the first arm.

Abstract: The thermal energy transfer techniques of the disclosed embodiments utilize passive thermal energy transfer techniques to reduce undesirable side effects of trapped thermal energy at the circuit level. The trapped thermal energy may be transferred through the circuit with thermally conductive structures or elements that may be produced as part of a standard integrated circuit process. The localized and passive removal of thermal energy achieved at the circuit level rather just at the package level is both more effective and more efficient.

Abstract: An integrated circuit (IC) provides a reset function. The IC receives a command that is defined by a first sequence of counts of signal transitions of a first signal during windows of a second signal and provides a reset function when it is determined that the command is received. A device including the IC and a system including the device are provided.

Abstract: A method that includes forming an opening between at least one first electrode and a second electrode by forming a recess in a first electrode layer, the recess having sidewalls that correspond to a surface of the at least one first electrode, forming a first sacrificial layer on the sidewalls of the recess, the first sacrificial layer having a first width that corresponds to a second width of the opening, forming a second electrode layer in the recess that corresponds to the second electrode, and removing the first sacrificial layer to form the opening between the second electrode and the at least one first electrode.

Abstract: A memory device includes a plurality of memory cells and programming circuitry configured to select a group of memory cells, receive a first data word and program memory cells of the selected group based on the data word. The memory device includes a program circuit configured to receive at least one second data word, and, for each second data word, send a program current in parallel to discriminated memory cells based on the corresponding second data word during a corresponding program phase. The memory device further includes an optimization circuit configured to generate the at least one second data word from the first data word. The number of discriminated memory cells of the second data word is maximized compatibly with a maximum predetermined limit of the total program current provided by the program circuit.