Abstract: A memory cell including a via made of a phase-change material arranged between a lower electrode and an upper electrode, wherein the via includes a first region adjacent to a second region itself adjacent to at least one third region, the first, second, and third regions each extending from the upper electrode to the lower electrode, the crystallization temperature of the second region ranging between that of the first region and that of the third region, and the melting temperatures of the first, second, and third regions being substantially identical.
Type:
Application
Filed:
September 4, 2013
Publication date:
March 13, 2014
Applicants:
Commissariat à I'Énergie Atomique et aux Énergies Alternatives, STMicroelectronics (Crolles 2) SAS
Abstract: A method of forming a semiconductor device is disclosed. The method including providing a substrate with at least one insulating layer disposed thereon, the at least one insulating layer including a trench; forming at least one liner layer on the at least one insulating layer; forming a nucleation layer on the at least one liner layer; forming a first metal film on a surface of the nucleation layer; etching the first metal film; and depositing a second metal film on the etched surface of the first metal film, the second metal film substantially forming an overburden above the trench.
Type:
Application
Filed:
September 11, 2012
Publication date:
March 13, 2014
Applicants:
STMICROELECTRONICS, INC., INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventors:
Lindsey H. Hall, Michael Hatzistergos, Ahmet S. Ozcan, Filippos Papadatos, Yiyi Wang
Abstract: Signals generated by an array of photodiodes are applied to the inputs of corresponding edge detection circuits. Each edge detection circuit generates an output that changes state in response to a detected edge of the photodiode generated signal. The edge detection circuits may be formed by toggle flip-flop circuits. The outputs of the edge detection circuits are logically combined using exclusive OR logic to generate an output. The exclusive OR logic may be formed by a cascaded tree of exclusive OR circuits.
Abstract: A method of fabricating a semiconductor device including providing a gate structure on a channel portion of a semiconductor substrate, wherein the gate structure includes at least one gate dielectric on the channel portion of the semiconductor substrate and at least one gate conductor on the at least one gate dielectric. An edge portion of the at least one gate dielectric is removed on each side of the gate structure, wherein the removing of the edge portion of the gate dielectric provides an exposed base edge of the at least one gate conductor and an exposed channel surface of the semiconductor substrate underlying the gate structure. The sidewall of the gate structure is oxidized, which also oxidizes at least one of the exposed base edge of the at least one gate conductor and the exposed channel surface of the semiconductor substrate that is underlying the gate structure.
Type:
Application
Filed:
November 20, 2013
Publication date:
March 13, 2014
Applicants:
STMICROELECTRONICS S.A., INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventors:
Erwan Dornel, Pascal R. Tannhof, Denis Rideau
Abstract: An embodiment of an integrated electronic device having a body, made at least partially of semiconductor material and having a top surface, a bottom surface, and a side surface, and a first antenna, which is integrated in the body and enables magnetic or electromagnetic coupling of the integrated electronic device with a further antenna. The integrated electronic device moreover has a coupling region made of magnetic material, which provides, in use, a communication channel between the first antenna and the further antenna.
Abstract: The disclosure relates to a test process of an image stabilization system in an image capture apparatus, comprising steps of: submitting the stabilization system to rotation vibratory movements around two distinct rotation axes, measuring characteristics of rotation vibratory movements, and setting the rotation vibratory movements to setpoint position values and, taking into consideration the measured characteristics of the vibratory movements, collecting images from the image capture apparatus submitted to vibration and analyzing the collected images.
Type:
Grant
Filed:
January 27, 2011
Date of Patent:
March 11, 2014
Assignee:
STMicroelectronics (Grenoble 2) SAS
Inventors:
Dominique Luneau, Paul Varillon, Remi Serve
Abstract: A method manufactures a capacitor having polycrystalline dielectric layer between two metallic electrodes. The dielectric layer is formed by a polycrystalline growth of a dielectric metallic oxide on one of the metallic electrodes. At least one polycrystalline growth condition of the dielectric oxide is modified during the formation of the polycrystalline dielectric layer, which results in a variation of the polycrystalline properties of the dielectric oxide within the thickness of said layer.
Abstract: An device and method of generating environmental reverberation effects for digital audio signals is presented. The device includes a reverberation controller. The reverberation controller pre-processes one or more predetermined characteristics of a first audio signal to produce a pre-processed signal and generates a plurality of delayed outputs from the pre-processed signal, each output having a predetermined delay. The reverberation controller also produces a plurality of reflection outputs from the plurality of delayed outputs and combines the plurality of reflection outputs to produce a second audio signal having a desired reverberation response.
Type:
Grant
Filed:
November 5, 2007
Date of Patent:
March 11, 2014
Assignee:
STMicroelectronics Asia Pacific PTE., Ltd.
Abstract: A method for authenticating a transmission between a first and a second circuit transiting through at least one third circuit, wherein: data are transmitted from the first to the third circuit, and from the third to the second circuit; a first signature of the data is calculated by the first circuit; at least a second signature of the data is calculated by the third circuit; at least one first portion of the first signature is transmitted by the first circuit to the third one; and the second signature is transmitted by the third circuit to the second one, a portion of this signature being distorted in case of a failure of authentication of the first portion of the first signature by the third circuit.
Type:
Grant
Filed:
July 25, 2011
Date of Patent:
March 11, 2014
Assignee:
STMicroelectronics (Rousset) SAS
Inventors:
Gilles Bas, Hervé Chalopin, François Tailliet
Abstract: A capped integrated device includes a semiconductor chip, incorporating an integrated device and a protective cap, bonded to the semiconductor chip for protection of the integrated device by means of a bonding layer made of a bonding material. The bonding material forms anchorage elements within recesses, formed in at least one between the semiconductor chip and the protective cap.
Abstract: The present disclosure relates to a method of adjusting the resonance frequency of a vibrating element, comprising measuring the resonance frequency of the vibrating element, determining, using abacuses and as a function of the resonance frequency measured, a dimension and a position of at least one area of modified thickness to be formed on the vibrating element so that the resonance frequency thereof corresponds to a setpoint frequency, and forming on the vibrating element, an area of modified thickness of the determined dimension and position.
Abstract: A memory and a method for controlling a memory including: a set of first memory blocks of identical size, intended to contain first words, a set of second memory blocks of identical size, intended to contain second words, the number of second words being identical to the number of first words, a third memory block identical to the first blocks, a fourth memory block identical to the second blocks, each memory address comprising a first portion identifying a same line in all blocks, and each first word of the third block identifying a free word from among the second words sharing a same second address portion.
Abstract: A scheduler device schedules executions of jobs using resources of a computational grid. The scheduler is configured for identifying an equilibrium threshold between resources and jobs. Below the equilibrium threshold, the scheduler schedules the execution of the jobs using the resources of the computational grid according to Pareto-optimal strategies. Above the equilibrium threshold, the scheduler schedules the execution of the jobs using the resources of the computational grid according to Nash-equilibrium strategies.
Abstract: An electronic device includes a capacitive component with variable capacitance coupled to a control stage that controls the capacitance, based on a reference signal, with a reference frequency, and an excitation signal, that is a multiple of the reference frequency. The capacitive component includes a variable capacitive network having a plurality of switched capacitors, each being switchable between a first configuration, where it is connected between connection terminals of the capacitive component, and a second configuration, where it is connected at most to one of the connection terminals. The control stage includes a logic module, coupled to the variable capacitive network for switching periodically each capacitor between the first configuration and the second configuration. A sign circuit, coupled to the capacitive component supplies a control signal having edges concordant with the excitation signal in one half-period of each cycle of the reference signal and discordant edges in the other half-period.
Abstract: A driving circuit has output terminal connected to an ultrasonic transducer and provides an output voltage. The driving circuit includes an output transistor coupled between a voltage reference and the output terminal, a high voltage comparator coupled to said output terminal and to a threshold voltage reference), a start-up circuit controlled by a setting signal; and a switching ON/OFF circuit having an input coupled to the start-up circuit an input coupled to the comparator, and an output coupled to a control terminal of the output transistor. The start-up circuit provides an ON signal to the switching on/off circuit and the comparator provides an OFF signal to the switching on/off circuit which switches off the output transistor. The high voltage comparator generates the switching off signal in response to the output voltage reaching a desired supply voltage value which depends on the value of the first threshold voltage reference.
Abstract: Methods and systems are described for enabling improved interface between a dual-mode multimedia source that supports a pair of data formats and a sink device operable using inputs in a third data format. An adaptor device enabling improved connectivity as well as backward compatibility with legacy devices is disclosed. The system enables the transmission of sideband channel configured in an I2C over AUX format thereby enabling increased performance in sideband channels of a dual-mode source.
Abstract: An imaging device may be formed in a semiconductor substrate including a matrix array of photosites extending in a first direction and a second direction. The imaging device may include a transfer module configured to transfer charge in the first direction and an extraction module configured to extract charge in the second direction.
Abstract: A packaging scheme for MEMS device is provided. A method of packaging MEMS device in a semiconductor structure includes forming an insulation fence that surrounds the MEMS device on the semiconductor structure. The method further includes attaching a wafer of dielectric material to the insulation fence. The lid wafer, the insulation fence, and the semiconductor structure enclose the MEMS device.
Abstract: In a multi-phase power supply voltage regulator functioning at a nominal switching frequency, one or more phases are kept off for optimizing energy efficiency at relatively low load conditions. Reactivation of stand-by phases in response to a load increase transient is made more efficiently by exploiting information already present in the output voltage control loop. The technique comprises a) deriving from the control loop information on the equivalent nominal switching frequency given by the product of the nominal switching frequency by the number of active phases; b) updating at every beat of a clock signal the instantaneous value of the equivalent switching frequency; c) determining the band of equivalent switching frequency values to which the instantaneous value belongs; d) logically combining the equivalent switching frequency information with a determined band of output current level, for switching on one or more stand-by phases in response to a load increase transient.
Abstract: A packaged device, wherein at least one sensitive portion of a chip is enclosed in a chamber formed by a package. The package has an air-permeable area having a plurality of holes and a liquid-repellent structure so as to enable passage of air between an external environment and the chamber and block the passage of liquids.
Type:
Application
Filed:
August 29, 2013
Publication date:
March 6, 2014
Applicant:
STMicroelectronics S.r.l.
Inventors:
Federico Giovanni Ziglioli, Fulvio Vittorio Fontana, Luca Maggi