Abstract: A gyroscope includes a body, a driving mass, which is mobile according to a driving axis, and a sensing mass, which is driven by the driving mass and is mobile according to a sensing axis, in response to rotations of the body. A driving device forms a microelectromechanical control loop with the body and the driving mass and maintains the driving mass in oscillation with a driving frequency. The driving device comprises a frequency detector, which supplies a clock signal at the frequency of oscillation of the driving mass, and a synchronization stage, which applies a calibrated phase shift to the clock signal so as to compensate a phase shift caused by components of the loop that are set between the driving mass and the control node.
Type:
Application
Filed:
May 3, 2013
Publication date:
September 19, 2013
Applicant:
STMicroelectronics S.r.l.
Inventors:
Luciano Prandi, Carlo Caminada, Alessandra Maria Rizzo Piazza Roncoroni
Abstract: A nozzle plate for a fluid-ejection device, comprising: a first substrate made of semiconductor material, having a first side and a second side; a structural layer extending on the first side of the first substrate, the structural layer having a first side and a second side, the second side of the structural layer facing the first side of the first substrate; at least one first through hole, having an inner surface, extending through the structural layer, the first through hole having an inlet section corresponding to the first side of the structural layer and an outlet section corresponding to the second side of the structural layer; a narrowing element adjacent to the surface of the first through hole, and including a tapered portion such that the inlet section of the first through hole has an area larger than a respective area of the outlet section of the first through hole.
Abstract: An integrated circuit protected against electrostatic discharges, having output pads coupled to amplification stages, each stage including, between first and second power supply rails, a P-channel MOS power transistor in series with an N-channel MOS power transistor, this integrated circuit further including protection circuitry for simultaneously turning on the two transistors when a positive overvoltage occurs between the first and second power supply rails.
Abstract: An embodiment of an electronic system may be provided so as to have superior coupling by implementing a communication mechanism that provides at least for horizontal communication for example, on the basis of wired and/or wireless communication channels, in the system. Hence, by enhancing vertical and horizontal communication capabilities in the electronic system, a reduced overall size may be achieved, while nevertheless reducing complexity in PCBs coupled to the electronic system. In this manner, overall manufacturing costs and reliability of complex electronic systems may be enhanced.
Abstract: A process for manufacturing semiconductor packages is provided, that includes drilling blind apertures in a reconstituted wafer, adhering a dry film resist on the wafer over the apertures, and patterning the film to expose a space around each of the apertures. The apertures and spaces are then filled with conductive paste by wiping a quantity of the paste across a surface of the film so that paste is forced into the spaces and apertures. The spaces around the apertures define contact pads whose thickness is constrained by the thickness of the film, preferably to about 10 ?m or less. To prevent paste from trapping air pockets in the apertures, the wiping process can be performed in a chamber from which much or all of the air has been evacuated. After curing the paste, the wafer is thinned from the back to expose the cured paste in the apertures.
Abstract: Aspects of the invention are directed towards an apparatus and method for detecting conventional and exotic cadences in video sequences. The cadence detector includes a motion auto-correlation unit using the inter-frame/field motion information to detect the cadence and a motion cross-correlation unit using the inter-frame/field motion information and the detected cadence to determine the cadence phase. The cadence detector also may include a reset signal generator to generate a reset signal to control the motion auto-correlation unit and the motion cross-correlation unit. The exotic cadence detector is robust and may support many cadences with reduced cadence detection latency as compared to the prior art.
Type:
Grant
Filed:
December 23, 2010
Date of Patent:
September 17, 2013
Assignee:
STMicroelectronics Asia Pacific Pte Ltd.
Abstract: An embodiment of a memory device of SRAM type integrated in a chip of semiconductor material is proposed. The memory device includes a plurality of memory cells each for storing a binary data having a first logic value represented by a first reference voltage or a second logic value represented by a second reference voltage. Each memory cell includes a bistable latch—having a main terminal, a complementary terminal, a set of field effect main storage transistors coupled to the main terminal for maintaining the main terminal at the reference voltage corresponding to the stored logic value or to a complement thereof, a set of field effect complementary storage transistors coupled to the complementary terminal for maintaining the complementary terminal at the reference voltage corresponding to the complement of the logic value associated with the main terminal—and a field effect access transistor for accessing the main terminal.
Abstract: A method for making a silicon layer extending on an insulation layer, including the steps of forming a silicon-germanium layer on at least a portion of a silicon wafer; transforming portions of the silicon-germanium layer into porous silicon pads; growing a monocrystalline silicon layer on the silicon-germanium layer and on the porous silicon pads; removing the silicon-germanium layer; oxidizing the porous silicon pads; and depositing an insulation material on the silicon layer.
Abstract: A method of determining, by a first device capable of transmitting a two-state signal over a single-wire connection to a second device, the binary state of data transmitted by the second device over said connection, the state being determined according to the slope of a rising edge of the two-state signal.
Abstract: Small phase change memory cells may be formed by forming a segmented heater over a substrate. A stop layer may be formed over the heater layer and segmented with the heater layer. Then, sidewall spacers may be formed over the segmented heater to define an aperture between the sidewall spacers that may act as a mask for etching the stop layer over the segmented heater. As a result of the etching using the sidewall spacers as a mask, sublithographic pore may be formed over the heater. Phase change material may be formed within the pore.
Abstract: The trend toward moving to digital content is progressing and expanding every day. With that trend comes the availability of a multitude of content from many content sources. There is a need for this content to be distributed to multiple destinations, and there is a further need to have the content synchronized among those multiple destinations. Embodiments described herein detail a method of synchronizing this content in an asynchronous environment, such as a powerline network, including using a PHY timing flag that is used to compensate for PHY-to-channel-to-PHY delays.
Abstract: A system for exchanging information in an on-chip communication network using optical flow information for communication between Intellectual Property cores. The information is exchanged between a plurality of initiators and targets in the Intellectual Property cores. The system includes a router for propagating optical flow information from the initiators to the targets. Each initiator includes an interface to convert the traffic generated by the initiator and transmit it in the form of an optical flow within the on-chip communication network, and each target includes an interface to convert information from the optical form into the electrical form. The system is organized as a parametric system and includes programming module to define a first set of high level parameters, a second set of initiator network interface parameters and a third set of target network interface parameters.
Type:
Grant
Filed:
July 26, 2012
Date of Patent:
September 17, 2013
Assignee:
STMicroelectronics s.r.l.
Inventors:
Alberto Scandurra, Giovanni Strano, Carmelo Pistritto
Abstract: A vertical bidirectional protection diode including, on a heavily-doped substrate of a first conductivity type, first, second, and third regions of the first, second, and first conductivity types, these regions all having a doping level greater than from 2 to 5×1019 atoms/cm3 and being laterally delimited by an insulated trench, each of these regions having a thickness smaller than 4 ?m.
Abstract: A method is for choosing a mode out of a set of functioning modes of an integrated circuit (IC) device powered from different supply voltages from respective supply nodes. The IC device may include a mode pin for determining a functioning mode of the device, an internal control circuit coupled to the supply nodes and to the mode pin for sensing an electrical value on the mode pin and to start the IC device in a respective functioning mode depending on the supply node that is powered first. The method may include identifying the different supply voltage that first exceeds a threshold voltage, when the internal control circuit is powered, sensing the electrical value on the mode pin, and powering circuits of the IC device from the different supply voltage that first exceeded the threshold voltage and starting the device in a functioning mode determined by a value of the electrical value sensed on the mode pin and by the different supply voltage that first exceeded the voltage threshold.
Type:
Grant
Filed:
December 20, 2010
Date of Patent:
September 17, 2013
Assignee:
STMicroelectronics S.R.L.
Inventors:
Alberto Gussoni, Ambrogio Bogani, Luigino D'Alessio, Paolo Pascale
Abstract: In one embodiment, a method for converting an analog input value to a digital output value is disclosed. A successive approximation is performed. The analog input is quantized to a first quantized value, which is converted to a first analog value using a DAC. The first analog value is subtracted from the analog input value to form a first residue. The first residue is quantized to form a second quantized value, and a second residue is formed by converting the second quantized value to a second analog value using the DAC and subtracting the second analog value from the first residue value. The second residue is then quantized to form a third quantized value. The first, second and third quantized values are converted into a digital output value. The first, second and third quantized values each have at least three levels.
Type:
Grant
Filed:
December 20, 2011
Date of Patent:
September 17, 2013
Assignee:
STMicroelectronics R & D (Shanghai) Co., Ltd.
Abstract: A parallel deblocking filtering method, and deblocking filter processor performing such deblocking, for removing edge artifacts created during video compression. The method includes loading luma samples for a macroblock. Filtering is performed on a set of vertical edges of the macroblock using information in the luma samples, with vertical edge filtering occurring concurrently with the loading of the luma samples. The method also includes filtering a set of horizontal edges of the macroblock using information in the luma samples. The horizontal edge filtering occurs in parallel with vertical edge sampling and with loading operations. The use of parallel and concurrent operations significantly enhances the efficiency of the deblocking method. Storing of filtered samples is also performed in the method, and this storing is performed concurrently with some loading operations as well as filtering operations. Edge filtering includes performing filtering to the H.264 standard and its deblocking filtering algorithm.
Abstract: Wheatstone bridges, each formed of four identical resistors, are used as integrated circuit identification elements. An identification circuit including an assembly of Wheatstone bridges and comparators is formed in a substrate. Since the resistors forming the bridges are sensitive to technological dispersions, the output voltages of the bridges are not identical. Each comparator compares the outputs of two bridges and provides a bit of an identification number of the chip. Preferably, the resistors are covered with insulator only, at least up to a second interconnect level from the substrate.
Abstract: The imaging device has an imaging surface and a sensor, wherein the imaging surface is illuminated and reflects at least some of the illumination to the sensor to detect an image. The imaging device has a width and an optical path passing therethrough, wherein the optical path exhibits distortion as a result of the width of the device and the nature of the optical path. The imaging device includes an optical element which in use compensates for the distortion by generating a magnification profile across a tangential plane of the device at the sensor.
Abstract: A media storage device may store content adapted to be inserted in a media reader for reading the content. The content may be encrypted, and the media storage may include a smart object physically attached to the media storage and arranged to be read by a smart object reader of the media reader. The smart object may include security information for decrypting the content in the smart object reader.
Abstract: A method of fabricating a semiconductor device including providing a gate structure on a channel portion of a semiconductor substrate, wherein the gate structure includes at least one gate dielectric on the channel portion of the semiconductor substrate and at least one gate conductor on the at least one gate dielectric. An edge portion of the at least one gate dielectric is removed on each side of the gate structure, wherein the removing of the edge portion of the gate dielectric provides an exposed base edge of the at least one gate conductor and an exposed channel surface of the semiconductor substrate underlying the gate structure. The sidewall of the gate structure is oxidized, which also oxidizes at least one of the exposed base edge of the at least one gate conductor and the exposed channel surface of the semiconductor substrate that is underlying the gate structure.
Type:
Application
Filed:
May 18, 2012
Publication date:
September 12, 2013
Applicants:
STMICROELECTRONICS S.A., INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventors:
Erwan Dornel, Pascal R. Tannhof, Denis Rideau