Abstract: An electrostatic discharge protection circuit is coupled to a power supply rail and a ground supply rail of an integrated circuit and includes at least one shunt configured to couple the supply rails and a trigger configured to supply on an output a shunt control voltage to a control terminal of the shunt to set the shunt in a coupling state when an ESD event is sensed on one of the supply rails. The protection circuit further comprises a voltage booster arranged between the output of the trigger and the control terminal of the shunt to boost the shunt control voltage.

Abstract: A plurality of circuits in a same package including a first integrated circuit having at least one NFC-type communication interface and at least one communication interface of another type, and a second integrated circuit having a security module with a non-volatile memory, the non-volatile memory being used by the NFC interface to store configuration data.

Abstract: A mobile device including: a battery; an element for charging the battery; a near-field communication circuit; and a connection between the near-field communication circuit and the battery charge element.

Abstract: A secure memory includes a bistable memory cell having a programmed start-up state, and means for flipping the state of the cell in response to a flip signal. The memory may include a clock for generating the flip signal with a period, for example, smaller than the acquisition time of an emission microscope.

Abstract: Methods and systems are described for displaying enabling the transmission, formatting, and display of multimedia data after a hot plug event during a start-up dead period. In particular, approaches for transmission, formatting, and display of multimedia data in the absence or non-operation of a hot plug detect system or signal, so that multimedia information can be displayed in a proper format even during the dead period when no hot plug detect signal is received.

Abstract: A method for measuring the voltage of a battery of an electronic device by means of a measurement device integrated to the electronic device, wherein, after the connection of the battery to the electronic device, the measurement device prevents battery charge and discharge operations during the measurement.

Abstract: A sensor assembly includes: an electrically insulating and flexible body (13), in the form of a plate having a first face (13a) and a second face (13b); and a first sensor (15; 315) and a second sensor (17), which are incorporated in the body (13). The first sensor (15) is set between the first face (13a) and the second sensor (17), and the second sensor (17) is set between the first sensor (15) and the second face (13b).

Abstract: A method for real-time quantitative detection of single-type, target nucleic acid sequences amplified using a PCR in a microwell, comprising introducing in the microwell a sample comprising target nucleic acid sequences, magnetic primers, and labelling probes; performing an amplification cycle to form labelled amplicons; attracting the magnetic primers to a surface through a magnetic field to form a layer including labelled amplification products and free magnetic primers; and detecting the labelled amplification products in the layer with a surface-specific reading method.

Abstract: A hydrogen-oxygen fuel cell including an electrolyte sandwiched between two catalyst layers or sheets, each catalyst layer or sheet being in contact with a porous electrode, in which one or several catalyst layers or sheets and one or several electrode layers or sheets interpenetrate.

Abstract: A variable latency interface and method for managing variable latency. An apparatus includes a storage device controller and a read/write channel coupled to the storage device controller by a variable latency interface. The variable latency interface includes a media control component configured for read and write operations. The variable latency interface also includes a data transfer component configured for read and write operations. A read or write operation in the media control component is offset from a respective read or write operation in the data transfer component by a latency period.

Abstract: An electronic device includes a first semi-conductor die, a second semi-conductor die and an electrically conductive element. The electrically conductive element includes a first electrically conductive part interposed at least partially between the first semi-conductor die and the second semi-conductor die, wherein said first part is electrically coupled to the first semi-conductor die. The electrically conductive element further includes a second electrically conductive part electrically coupled to the first part, wherein said second part extends from at least part of the first part. The first part is an electrically conductive strap between the dice, and the second part is clip extending from at least part of the strap.

Abstract: A method for transmitting messages from first units of an integrated circuit to at least one second unit of the integrated circuit. The first units generate first digital messages and transform them into second digital messages obtained by application of an orthogonal or quasi-orthogonal transformation to the first messages. The second messages of the first units are added up and transmitted to the second unit.

Abstract: A package includes a die and at least one further die. The die has an interface configured to receive a transaction request from the further die via an interconnect and to transmit a response to the transaction request to said further die via the interconnect. The die also has mapping circuitry which is configured to receive the transaction request including at least first source identity information, wherein the first source identity information is associated with a source of the transaction request on the further die. The mapping circuitry is configured to modify the transaction request to replace the first source identity information with local source identity information, wherein that local source identity information is associated with the mapping circuitry. The mapping circuitry is configured to modify the received transaction request to provide said first source identity information in a further field.

Abstract: An image processing apparatus suitable for processing a digital image in YCrCb color space, the image having an initial luminance plane Y and two initial Cr, Cb chrominance planes, the processing apparatus including a first block that receives the initial luminance plane Y of the digital image and processes and modifies the initial luminance plane Y in order to provide a modified luminance plane Y in output; a color artifact correction block, operating in parallel with the first block, the correction block receiving the initial planes Y, Cr, Cb of the image and modifying the initial chrominance planes Cr and Cb through a pixel by pixel processing approach with a mobile working window, the correction block having a false colors correction sub-block and a purple fringing correction sub-block, or both, the sub-blocks structured to modify values of the initial Cr, Cb chrominance planes based on information contained in the initial Cr, Cb chrominance planes and also based on information contained in the initial lu

Abstract: Parallelization of decoding of a data stream encoded with a variable length code includes determining one or more markers, each of which indicates a position within the encoded data stream. The determined markers are included into the encoded data stream together with the encoded data. At the decoder side, the markers are parsed from the encoded data stream and based on the extracted markers. The encoded data is separated into partitions, which are decoded separately and in parallel.

Abstract: A method of protection from noise of a digital signal generated by a comparator, including the steps of generating an output signal that switches from a first logic state to a second logic state at a first switching of logic state of the digital signal; detecting a change from the first logic state to the second logic state of the output signal; and inhibiting further switchings of the output signal for a first time interval after the change from the first logic state to the second logic state.

Abstract: A technique for selecting instructions for execution from an issue queue at multiple function units while reducing the chances of instruction collisions. In an embodiment, each function unit in a processor may include a selection logic circuit that selects a specific instruction from the issue queue for execution. In order to avoid instruction collision, a function unit may have a selection logic circuit that may select two instructions from an instruction queue: one according to a first selection technique and one according to a second selection technique. Then, by comparing the instruction selected by the first selection technique to the instruction selected by the selection logic circuit of another function unit, the instruction selected by the second technique may be used instead if there will be an instruction collision because the instruction selected by the first selection technique is the same as the instruction selected at a different function unit.

Abstract: Integrated-circuit chips are fabricated according to a process wherein weak portions are formed in a substrate wafer surrounding a plurality of locations. An integrated-circuit chip is defined at each location by destroying the weak portions so as to singulate integrated-circuit chips.

Abstract: A method for forming a resonator including a resonant element, the resonant element being at least partly formed of a body at least partly formed of a first conductive material, the body including open cavities, this method including the steps of measuring the resonator frequency; and at least partially filling said cavities.

Abstract: A MEMS resonant accelerometer is disclosed, having: a proof mass coupled to a first anchoring region via a first elastic element so as to be free to move along a sensing axis in response to an external acceleration; and a first resonant element mechanically coupled to the proof mass through the first elastic element so as to be subject to a first axial stress when the proof mass moves along the sensing axis and thus to a first variation of a resonant frequency. The MEMS resonant accelerometer is further provided with a second resonant element mechanically coupled to the proof mass through a second elastic element so as to be subject to a second axial stress when the proof mass moves along the sensing axis, substantially opposite to the first axial stress, and thus to a second variation of a resonant frequency, opposite to the first variation.