Abstract: A vertical power component including a silicon substrate of a first conductivity type and, on the side of a lower surface supporting a single electrode, a well of the second conductivity type, in which the component periphery includes, on the lower surface side, a peripheral trench at least partially filled with a passivation and, between the well and the trench, a porous silicon insulating ring.

Abstract: A complementary read-only memory (ROM) cell includes a transistor; and a bit line and a complementary bit line adjacent to the transistor; wherein a drain terminal of the transistor is connected to one of the bit line and the complementary bit line based on data programmed in the ROM cell.

Abstract: A control device for a matrix plasma display screen has a row driver circuit capable of sequentially selecting the rows of the matrix and a column driver circuit, for each column of the matrix, with an individual column driver unit that has at least a first transistor of the MOS type capable of emitting, towards each column of a desired set of columns, a state change signal in order to allow the transition of the set from a first state towards a second state, and a controller.

Abstract: A memory architecture includes a plurality of local input and output circuitries, with each local input and output circuitry associated with at least one memory bank. The memory architecture also includes a global input and output circuitry, which includes a plurality of global sub-write circuitries, is coupled to the plurality of local input and output circuitries One global sub-write circuitry is enabled and provides a write-data to a selected local input and output circuitry.

Abstract: A process for producing a microelectronic device includes producing a first semiconductor substrate which includes a first layer and a second layer present between a first side and a second side of the substrate. First electronic components and an interconnecting part are produced on and above the second side. The substrate is then thinned by a first selective etch applied from the first side and stopping on the first layer followed by a second selective etch stopping on the second layer. A second substrate is attached over the interconnecting part. The electronic components may comprise optoelectronic devices which are illuminated through the second layer.

Abstract: A device for calculating the quotient q and remainder r of the division (y·k1+x)/k2, wherein k1 and k2 are integers and constant, and wherein x and y are integers. The device comprises a first digital circuit for receiving as input values of y and identifying corresponding values of the quotient qy and the remainder ry of the function y·k1/k2, a second digital circuit for calculating the remainder r of the division, by a) calculating a combined value (x+ry) of the remainder ry and the value of x, b) verifying if the combined value (x+ry) is less than k2, c) correcting the combined value (x+ry) if the verification indicates that the combined value (x+ry) is not less than k2, and d) assigning the corrected combined value (x+ry) to the remainder r, a third digital circuit for calculating the quotient q of the division, by a) correcting the quotient qy if the verification (2206) indicates that the combined value (x+ry) is not less than k2, and b) assigning the corrected quotient qy to the quotient q.

Abstract: An optical navigation device includes an optical transmission element, operable in use to transmit light from an illumination source to a sensor via a mousing surface, and a housing unit. The optical transmission element may have an alignment shaft. Ideally the optical transmission element and housing unit are assembled to a substrate by snap-fit. The alignment shaft ensures that the optics are properly aligned to the substrate and the light source and sensor thereon.

Abstract: This system for processing digital data may include a set of slave processing units for the execution of elementary functions, an interconnection module, which is designed to communicate with a data transfer network and to transfer data between the processing units, on the one hand, and the data transfer network, on the other hand, and a controller controlling the interconnection module to control the data transfer.

Abstract: A secure Universal Serial Bus (USB) storage device includes a memory controller capable of storing data in and retrieving data from a memory. The secure USB storage device also includes a USB secure microcontroller capable of authorizing access to the memory through the memory controller to thereby secure the memory. The USB secure microcontroller is also capable of protecting the data stored in the memory to thereby secure contents of the memory. The USB secure microcontroller could include an SPI interface and/or a GPIO interface emulating one or more of an SPI interface and an MMC interface to the memory controller. The memory controller could include an SPI interface and/or an MMC interface to the USB secure microcontroller. The secure USB storage device may be enumerated by a USB host controller under one or more device classes.

Abstract: A graphic system having a central processing unit; a system memory coupled to the central processing unit; a display unit provided with a corresponding screen; a graphic module coupled to and controlled by the central processing unit to render an image on the screen of the display unit, the graphic module including a fragment graphic module having a depth test buffer for storing a current depth value; a depth test stage coupled to the depth test buffer for comparing the current depth value with a depth coordinate associated with an incoming fragment and defining a resulting fragment; a test stage for testing the resulting fragment and defining a retained fragment; a buffer writing stage operatively associated with the test stage for receiving the retained fragment, the buffer writing stage coupled to the depth test buffer for updating the current depth value with a depth value of the retained fragment.

Abstract: A sync signal generator for a capacitive sensor includes a charge amplifier having an input for coupling to an inactive receive line in the capacitive sensor, a first comparator having a first input for receiving a first threshold voltage, a second input coupled to an output of the charge amplifier, and an output for providing a first sync signal, and a second comparator having a first input for receiving a second threshold voltage, a second input coupled to the output of the charge amplifier, and an output for providing a second sync signal. The charge amplifier includes an operational amplifier having a feedback circuit including a capacitor and a switch. The first threshold voltage is provided by a first digital-to-analog converter, and the second threshold voltage is provided by a second digital-to-analog converter.

Abstract: An integrated circuit is formed having an array of memory cells located in the dielectric stack above a semiconductor substrate. Each memory cell has two adjustable resistors and two heating elements. A dielectric material separates the heating elements from the adjustable resistors. One heating element alters the resistance of one of the resistors by applying heat thereto to write data to the memory cell. The other heating element alters the resistance of the other resistor by applying heat thereto to erase data from the memory cell.

Abstract: An amplifier circuit includes an amplifier unit that is configured to receive an input signal and generate a switching output signal. A level shifter is configured to shift the amplitude of the input signal to have a shifted amplitude that is proportional to a peak-to-peak amplitude of the switching output signal.

Abstract: A common-mode filter including, in series between a first input terminal and a first output terminal, a first and a second positively coupled inductive elements; in series between a second input terminal and a second output terminal, a third and a fourth positively coupled inductive elements; and in series between each midpoint of said series connections of inductive elements and the ground, a capacitive element and a fifth inductive element.

Abstract: A system for testing multi-clock domains in an integrated circuit (IC) includes a plurality of clock sources coupled to a plurality of clock controllers. Each of the clock sources generates a fast clock associated with one of the multi-clock domains. Each of the clock controllers is configured to provide capture pulses to test one clock domain. The capture pulses provided to a clock domain are at a frequency of a fast clock associated with the clock domain. The clock controllers operate sequentially to provide the capture pulses to test the clock domains.

Abstract: A semiconductor structure including a substrate of semiconductor material of a first type of conductivity; a first semiconductor layer set in direct electrical contact with the substrate on a first side of the substrate; a second semiconductor layer set in direct electrical contact with the substrate on a second side of the substrate; a first active electronic device formed in the first semiconductor layer; and a second active electronic device formed in the second semiconductor layer.

Abstract: An electronic trimming circuit carries out a trimming operation on portions of an integrated device. The circuit includes N trimmable interconnected resistances, each connected in parallel to a respective shunt fuse. N trimming transistors are each connected to a respective one of the shunt fuses to force therethrough substantially the whole current flowing in the respective trimming transistor. N bias networks are each functionally connected to a control terminal of a respective one of the trimming transistors to directly bias an active junction thereof. An externally driven heating device is thermally coupled with the active junctions of the trimming transistors adapted to raise the temperature thereof.

Abstract: Solder joint reliability in an integrated circuit package is improved. Each terminal of a quad, flat, non-leaded integrated circuit package is formed having portions that define a solder slot in the bottom surface of the terminal. An external surface of the die pad of the integrated circuit package is also formed having portions that define a plurality of solder slots on the periphery of the die pad. When solder is applied to the die pad and to the terminals, the solder that fills the solder slots increases the solder joint reliability of the integrated circuit package.

Abstract: A memory includes memory cells, data lines, block select lines, and selection circuitry. The data lines provide data to and from the memory cells and may be grouped into blocks. Each block includes data lines. Each of the block select lines is associated with a respective one of the blocks. The selection circuitry is select a block in response to a respective block select line and the memory performs a memory operation using the selected bit line block.

Abstract: A mobile device including: a battery; an element for charging the battery; a near-field communication circuit; and a connection between the near-field communication circuit and the battery charge element.