Abstract: A method is for non-destructive reading of an information datum stored in a memory that includes a first wordline, a first bitline and a second bitline, and a first ferroelectric transistor, which is connected between the bitlines and has a control terminal coupled to the first wordline. The method includes applying to the first wordline a first reading electrical quantity, generating a first difference of potential between the first and second bitlines, generating a first output electrical quantity, and applying to the first wordline a second reading electrical quantity. The method further includes generating a second difference of potential between the first and second bitlines, generating a second output electrical quantity, and comparing the first and second output electrical quantities with one another. On the basis of a result of said comparison, the method includes determining the logic value of the information data.

Abstract: Logic data is written in a memory having a first word line and a first bit line, with the memory including a first memory cell having a first ferroelectric transistor. The first ferroelectric transistor includes a layer of ferroelectric material and has a first conduction terminal coupled to the first bit line, and a control terminal coupled to the first word line. The logic data is written based on biasing the control terminal of the first ferroelectric transistor at a first biasing value, biasing the first conduction terminal of the first ferroelectric transistor at a second biasing value different from the first biasing value, and generating a stable variation of the state of polarization of the layer of ferroelectric material of the first ferroelectric transistor to write the logic data in the first memory cell.

Abstract: A non-volatile memory device may be integrated in a chip of semiconductor material. The memory device may include circuitry for receiving a measure instruction for obtaining a numerical measure value of a selected one among a plurality of predefined memory operations of the memory device. The memory device may also include circuitry for enabling the execution of the selected memory operation in response to the measure instruction. The execution of the selected memory operation may generate a corresponding result. The memory device may further include circuitry for providing at least one time signal, different from the corresponding result, relating to the execution of each memory operation, and circuitry for determining the measure value according to the at least one time signal of the selected memory operation.

Abstract: A process for the production of hydrogen for micro fuel cells, comprises the successive steps of: continuously supplying a catalytic bed with an aqueous solution of sodium borohydride, the catalytic bed being made of at least one metal chosen among cobalt, nickel, platinum, ruthenium with obtainment of hydrogen and of a by-product comprising sodium metaborate, continuously recovering the hydrogen thus obtained and supplying, with said hydrogen as it is as obtained, a micro fuel cell which transforms hydrogen into electric energy. An apparatus provides continuous supply of hydrogen to a micro fuel cell. An integrated system structured for continuously producing and supplying hydrogen to a micro fuel cell and for converting the continuously supplied hydrogen into electric energy.

Abstract: A dual supply circuit uses a dual feedback control, single inductor, dual polarity boost architecture with a low side power FET for end of current recirculation sensing. A dual feedback system tracks the output voltage variations and a low side power FET end of current recirculation sensing utilizes the internal current limit sensing system. Logic defining the state of operations allows the regulator to operate in both single and dual mode to cater to wide application ranges. The positive boost regulator can be operated in a buck mode making the output voltage constant with high input supply.

Abstract: An oscillator having a plurality of operatively coupled ring oscillators arranged in hyper-matrix architecture. The operatively coupled ring oscillators are either identical or non-identical and are coupled through a common inverter or tail current transistors.

Abstract: A device for measuring the current flowing through a power transistor of a voltage regulator, the voltage regulator having an input voltage and providing a regulated output voltage and the power transistor coupled between the input and output voltages. The measuring device includes a further transistor adapted to mirror a portion of the current flowing through the power transistor, the further transistor and the power transistor have a first non-drivable terminal in common that is coupled to the input voltage. The measuring device also includes a circuit block to connect the second non-drivable terminals of the power and the further transistor and to provide an output current equal to the portion of the current flowing through the first transistor; the measuring device further including a circuit adapted to detect the output current of said circuit block.

Abstract: A method for manufacturing and for testing an integrated circuit, including the steps of forming, on the upper portion of the integrated circuit, a passivation layer including openings at the level of metal tracks of the last interconnect stack of the integrated circuit; forming, in the openings, first pads connected to second pads formed on the passivation layer by conductive track sections, the first pads being intended for the connection of the integrated circuit; testing the integrated circuit by bringing test tips in contact with the second pads; and eliminating at least a portion of at least one of the conductive track sections.

Abstract: An integrated circuit for a smart card includes a plurality of data buffers and a processor. In particular, the processor selectively allocates data buffers from the plurality thereof and exchanges data therewith based upon different types of data. As such, the processor advantageously changes the allocation of the buffers for different data types based upon various bandwidth constraints in a particular smart card environment to enhance bandwidth utilization.

Abstract: Circuitry for encrypting at least a part of an input data flow and generating a tag based on the input data flow with the same ciphering algorithm and the same key, the algorithm including iterative computations by at least two operation units, the circuitry including a pipeline including an input selection unit arranged to receive first data values to generate encryption sequences with the ciphering algorithm, second data values to generate temporary tags with the ciphering algorithm and an output of the pipeline; a first stage arranged to receive an output of the input selection unit and including at least a first operation unit; and a second stage arranged to receive an output of the first stage, including at least a second operation unit and providing the output of the pipeline.

Abstract: A resistive element having two vertical resistive portions placed in two holes formed in the upper portion of a substrate and a horizontal resistive portion placed in a buried cavity connecting the bottoms of the holes.

Abstract: A method and a device for protecting a security module connected to a near-field communication router in a telecommunication device, wherein a transmission between the router and the security module is only allowed in the presence of a radio frequency communication flow detected by the router.

Abstract: An embodiment relates to a method for the detection of texture of a digital image, including providing a raw data image of the image by means of Bayer image sensors, determining noise in at least a region of the raw data image and determining the texture based on the determined noise without using a high pass or low pass filter.

Abstract: A multichannel splitter formed from 1 to 2 splitters, wherein: an input terminal of a first 1 to 2 splitter defines an input of the multichannel splitter; the 1 to 2 splitters are electrically series-connected; and first respective outputs of the 1 to 2 splitters define output terminals of the multichannel splitter.

Abstract: Passive circuit elements are formed at surfaces of two integrated circuit wafers. The passive circuit elements are utilized to align the two integrated circuit wafers to form an integrated circuit wafer stack.

Abstract: An embodiment of a process for manufacturing a power semiconductor device envisages the steps of: providing a body of semiconductor material having a top surface and having a first conductivity; forming columnar regions having a second type of conductivity within the body of semiconductor material, and surface extensions of the columnar regions above the top surface; and forming doped regions having the second type of conductivity, in the proximity of the top surface and in contact with the columnar regions. The doped regions are formed at least partially within the surface extensions of the columnar regions; the surface extensions and the doped regions have a non-planar surface pattern, in particular with a substantially V-shaped groove.

Abstract: A method for charging the battery of a portable object by a telephone, comprising a step for contactless transmission of power from a charging device of the telephone to the portable object, inducing the charging of the battery of the portable object.

Abstract: A parallel deblocking filtering method, and deblocking filter processor performing such deblocking, for removing edge artifacts created during video compression. The method includes loading luma samples for a macroblock. Filtering is performed on a set of vertical edges of the macroblock using information in the luma samples, with vertical edge filtering occurring concurrently with the loading of the luma samples. The method also includes filtering a set of horizontal edges of the macroblock using information in the luma samples. The horizontal edge filtering occurs in parallel with vertical edge sampling and with loading operations. The use of parallel and concurrent operations significantly enhances the efficiency of the deblocking method. Storing of filtered samples is also performed in the method, and this storing is performed concurrently with some loading operations as well as filtering operations. Edge filtering includes performing filtering to the H.264 standard and its deblocking filtering algorithm.

Abstract: A method for encoding video signals subjects the signals to unbalanced multiple description coding. The unbalanced multiple description coding codes a video signal in a first high resolution packet and a second low resolution packet and represents, respectively a first high resolution description and a second low resolution description. The unbalanced multiple description coding step includes using different intra refresh periods for the first and second high resolution descriptions, with an intra refresh period for the second low resolution description shorter than the intra refresh period of the first high resolution description.

Abstract: An embodiment of a process for manufacturing a power semiconductor device envisages the steps of: providing a body of semiconductor material having a top surface and having a first conductivity; forming columnar regions having a second type of conductivity within the body of semiconductor material, and surface extensions of the columnar regions above the top surface; and forming doped regions having the second type of conductivity, in the proximity of the top surface and in contact with the columnar regions. The doped regions are formed at least partially within the surface extensions of the columnar regions; the surface extensions and the doped regions have a non-planar surface pattern, in particular with a substantially V-shaped groove.