Abstract: A method for decrypting the encrypted messages sent by a transmission device to a first electronic device associated with a first trusted authority and to a second electronic device (ME). In one embodiment, first and second tokens are generated and exchanged, respectively, by the first and second electronic devices, which then generate a joint decryption key in order to decrypt the encrypted message.

Abstract: A phase change memory device includes a bitline biasing unit; and a bitline selection unit connecting a selected bitline to the bitline biasing unit and disconnecting deselected bitlines from the bitline biasing unit in an operative condition. A bitline discharge unit is connected to the bitlines to discharge leakage currents in the bitlines. The bitline discharge unit has a voltage regulation unit and a plurality of bitline discharge switches coupled between the voltage regulation unit and a respective bitline. The bitline discharge switches are controlled to connect the deselected bitlines to the voltage regulation unit and to disconnect the selected bitline from the voltage regulation unit. The voltage regulation unit comprises a PMOS transistor coupled between a regulated voltage bus and a reference potential line. The regulated voltage bus is connected to the bitline discharge switches and the control terminal of the PMOS transistor is biased to a constant voltage.

Abstract: A dynamic element matching (DEM) scheme is implemented in a crawling code generator for converting a b-bit binary input code into a (2b?1)-bit digital output code. A random generator determines for every conversion step a direction. A decimal difference between the current and previous binary input is calculated. The new crawling output code is determined based on the previous crawling output code, the direction and the decimal difference. The DEM scheme is used in a digital-to-analog converter such that the crawling output code switches digital-to-analog converting elements that output analog signals that are then summed to be the final analog signal.

Abstract: Adaptive scaling digital techniques attempt to place the system close to the timing failure so as to maximize energy efficiency. Rapid recovery from potential failures is usually by slowing the system clock and/or providing razor solutions (instruction replay.) These techniques compromise the throughput. We present a technique to provide local in-situ fault resilience based on dynamic slack borrowing. This technique is non-intrusive (needs no architecture modification) and has minimal impact on throughput.

Abstract: A chip scale package (CSP) device includes a CSP having a semiconductor die electrically coupled to a plurality of solder balls. A can having an inside top surface and one or more side walls defines a chamber. The CSP is housed in the chamber and is attached to the inside top surface of the can. A printed circuit board is attached to the solder balls and to the one or more side walls to provide support to the CSP and to the can. The CSP may be a Wafer-Level CSP. The can may be built from a metallic substance or from a non-metallic substance. The can provides stress relief to the CSP during a drop test and during a thermal cycle test.

Abstract: A signal processor including an equalizer responsive to an input signal and to a parameter signal, said equalizer configured to provide an output signal to an electro-acoustical transducer for compensating a frequency response of said electro-acoustical transducer; a transducer element for monitoring at least a physical parameter of said electro-acoustical transducer, said transducer element configured to provide a transducer signal, a processor block responsive to said transducer signal, configured to provide said parameter signal.

Abstract: A plurality of resistive paths are coupled in parallel to a common node. A high side driver is operable responsive to first control signals to selectively supply current to certain ones of the resistive paths. A low side driver, including a plurality of selectively actuated current sink paths, is provided to sink current from the common node. A control logic circuit actuates a current sink path within the low side driver for each resistive path that is selectively supplied current by the high side driver. A substantially constant low side voltage drop through these sink paths is provided regardless of the number of resistive paths that are supplied current by the high side driver. A switched high side and low side configuration operating in an analogous way is also disclosed.

Abstract: A control apparatus for LED diodes includes a dimmer TRIAC electrically connected in series between a power supply and a LED lighting converter. The converter comprises a transformer, with a primary winding coupled with an input terminal and a secondary winding coupled with an output terminal, and a switch coupled to the primary winding to regulate the current through the primary winding and regulate the output voltage. The apparatus comprises a control device adapted to control said switch determining the on period and the off period of the switch to maintain constant the output current to supply said LED diodes. The apparatus comprises a detector connected to the secondary winding of the transformer and adapted to detect the conduction angle of the TRIAC; the control device is adapted to regulate the output current to supply said LED diodes in response to the TRIAC conduction angle detected by the detector.

Abstract: An imaging device includes a fixed focused lens, an image sensor having a image matrix of a plurality of pixels arranged on a semiconductor substrate and supplying image data, and electronic means for reading the image matrix. The image sensor also comprises at least two ambient light sensors arranged on the semiconductor substrate on opposite sides of the image matrix, and configured to capture an ambient light intensity through the fixed lens, and the electronic means is also configured to read the two ambient light sensors and to supply ambient light data and the image data.

Abstract: A video compression framework based on parametric object and background compression is proposed. At the encoder, an object is detected and frames are segmented into regions corresponding to the foreground object and the background. The encoder generates object motion and appearance parameters. The motion or warping parameters may include at least two parameters for object translation; two parameters for object scaling in two primary axes and one object orientation parameter indicating a rotation of the object. Particle filtering may be employed to generate the object motion parameters. The proposed methodology is the formalization of the concept and usability for perceptual quality scalability layer for Region(s) of Interest. A coded video sequence format is proposed which aims at “network friendly” video representation supporting appearance and generalized motion of object(s).

Abstract: A reference signal generator circuit for an analog-to-digital converter, the circuit having a signal-generation stage to generate a first reference signal on a first reference terminal, and a filtering circuit arranged between the generator stage and the analog-to-digital converter to determine a filtering of disturbance present on the first reference signal and supply at output on a second reference terminal a second filtered reference signal, the filtering circuit having a switching circuit to connect the first reference terminal to the second reference terminal directly during startup of the reference signal generator circuit and then through the filtering circuit once the startup step is terminated.

Abstract: A protection layer is coated or otherwise formed over the interconnect structure. The interconnect structure includes a metal line (such as top and bottom metal layers connected by a metal via) and a low-K material. The protection layer includes a vertically aligned dielectric or other material dispersed with carbon nanotubes. The protection layer could include one or multiple layers of carbon nanotubes, and the carbon nanotubes could have any suitable dispersion, alignment, and pattern in each layer of the protection layer. Among other things, the carbon nanotubes help to reduce or prevent damage to the interconnect structure, such as by reducing or preventing the collapse of the low-K material or delamination between the metal line and the low-K material.

Abstract: A variable gain amplifier having an input node, a variable current source including a control input coupled to the input node, first and second branches coupled in parallel between a first supply terminal and the variable current source, the first and second branches defining a differential pair arranged to be controlled by first and second differential gain signals and having first and second output terminals, one of the output terminals including an output node of the variable gain amplifier; and a potential divider having a middle node coupled to the first and second output terminals, wherein the middle node is also coupled to the input node by a capacitor.

Abstract: A portable housing capable of being carried by a certain person includes a circuit. The circuit includes a memory for storing private data concerning that certain person, a circuit operable to effectuate storage of the private data in the memory in a secure manner, and a processing unit operable to control access to the memory for purposes of reading private data concerning the certain person from the memory and storing private data concerning the certain person to the memory. The conditions under which access to the memory for read and write operations with respect to the private data is permitted are governed by parameters that are specified by the certain person to whom the stored private data concerns. A biometric sensor may also be included to capture identification information useful in implementing the operations for controlling access to the memory.

Abstract: A method for acquiring images using at least one CMOS-type sensor with four transistors including an acquisition node and a read node, where the read node can receive a compression signal, including a step of reading a reference state of the sensor; a reset step; an integration step, during which the sensor is exposed and during part of which the compression signal is applied to the read node; and a step of reading the data acquired during the integration step; the read node being, during the integration step, isolated from the acquisition node, except immediately before the application of the compression signal, at which time the acquisition node is connected to the read node long enough to enable a transfer of the charges present at the acquisition node to the read node.

Abstract: A fail-safe level shifter switching with high speed and operational for a wide range of voltage supply includes a cascode module, and one or more speed enhancer modules. The cascode module receives one or more input logic signal for generating a plurality of output signals with a reduced switching time. The speed enhancer modules are coupled to the cascode module for facilitating faster charging and discharging of nodes of the cascode module and improving the robustness and operating voltage range of cascode module.

Abstract: A pulse generator circuit is provided. The pulse generator circuit has an input adapted to receive an input electrical quantity and an output at which an output electrical quantity is made available. A transfer characteristic establishes a relationship between said input and said output electrical quantities. The pulse generator circuit is adapted to provide said output electrical quantity in the form of pulses having a predetermined shape, suitable to be used for UWB transmission. The transfer characteristic has substantially a same shape as that of said pulses. Moreover, a UWB modulating system exploiting the novel pulse generator is proposed.

Abstract: A CMOS single photon avalanche diode (SPAD) design uses conventional, or at least known, CMOS processes to produce a device having a breakdown region in which the main p-n junction is formed of a deep n-well layer, and optionally on the other side, a p-add layer. The SPAD may also have a guard ring region which comprises the p-epi layer without any implant. The SPAD may have curved or circular perimeters. A CMOS chip comprises SPADs as described and other NMOS devices all sharing the same deep n-well.

Abstract: A method and system of controlling access to a programmable memory including: allowing code to be written to the programmable memory in a first access mode; preventing execution of the code stored in the programmable memory in the first access mode; verifying the integrity of the code stored in the programmable memory; if the integrity of the code stored in the programmable memory is verified, setting a second access mode, wherein in the second access mode, further code is prevented from being written to the programmable memory, and execution of the code stored in the programmable memory is allowed.

Abstract: An apparatus includes a plurality of call controllers that are capable of establishing a plurality of communication sessions over a packet network using a plurality of signaling protocols. The apparatus also includes an application controller that is capable of supporting one or more supplementary services during each of the communication sessions. As particular examples, the application controller and at least one of the call controllers are capable of at least one of: placing at least one of the communication sessions on hold so a user may initiate another of the communication sessions, placing at least one of the communication sessions on hold so the user may accept another of the communication sessions, and establishing a conference using at least two of the communication sessions. The communication sessions may use a common signaling protocol or different signaling protocols.