Abstract: A system and method for optimizing power distribution in a closed system. In an electronic device, one may apply a plurality of driving algorithms for components that provide different variations functionality. Thus, each component may be operated according to one of several different algorithms depending on the level and manner of functionality needed. In this manner, the overall system may be optimized for any number of operating modes such that each component may conserve electrical power usage while still providing the needed functionality for specific components during each operating mode. Such an optimization assessment may be a function of an economic model applied to the system whereby functionality and components are assigned specific values and costs based on the required functionality for any given task. Thus, the amount of power available may be allocated in an efficient manner based on a cost-benefit analysis.

Abstract: An electronic device is provided with: a first electronic circuit, integrated in a first die; a second electronic circuit, integrated in a second die; and a galvanic isolator element, designed to insulate galvanically, and to enable transfer of signals between, the first electronic circuit and the second electronic circuit. The galvanic isolator element has: a transformer substrate, distinct from the first die and from the second die; and a galvanic-insulation transformer formed by a first inductive element, integrated in the first die, and by a second inductive element, integrated in the transformer substrate and so arranged as to be magnetically coupled to the first inductive element.

Abstract: A circuit comprising: a device determiner configured to, in a first mode of operation, receive a device selection signal via at least one of: at least one control line and at least one signal line; and a device router configured to, in a second mode of operation, route signals between the at least one of: at least one control line and at least one signal line and at least one device dependent on the device selection signal.

Abstract: A system and method for reducing warpage of a semiconductor wafer. The system includes a device for securing the semiconductor wafer in a heating area. The device includes a holding mechanism for securing an edge of the semiconductor wafer. The device further includes a pressure reducing device that reduces the pressure underneath the semiconductor device, which further secures the semiconductor device in the heating area. The heating area includes a plurality of heating and cooling zones in which the semiconductor wafer is subjected to various temperatures.

Abstract: A voltage booster device may include a plurality of multiplication stages arranged in a sequence so that an input terminal of each multiplication stage, with the exception of a first multiplication stage, is connected to an output terminal of a previous multiplication stage. Each multiplication stage may include pumping circuitry for accumulating an electric charge proportional to a pump voltage value of the multiplication stage. Each multiplication stage may also include a phase signal generating circuit for switching the multiplication stages between a transfer phase and a maintaining phase. In at least one of the stages, the pumping circuitry may include at least two series connected charge accumulators. A terminal may be shared between the charge accumulators and may be connected through biasing circuitry to an output terminal of a previous multiplication stage for forcing the charge accumulators within a threshold potential drop value.

Abstract: Systems and methods are disclosed for determining the perceptibility of noise in a block of images and/or video. The systems and methods may compute a mask value for the block using a block masking generator. The mask value may indicate the perceptibility of noise in the block. The mask value may be computed using a normalized activity value and/or a texture value for the block. The normalized activity value may indicate the relative activity in the block as compared to the activity in the image and/or video. The texture value may indicate the strength and/or number of edges in the block.

Abstract: Motion estimation systems and methods are disclosed. An apparatus may include a processing unit to acquire video images and to arrange the video images into a plurality of sequential video frames, and a motion estimation unit that receives the sequential video frames and determines a set of repetitive pattern neighbor candidate vectors for repetitive pattern content in a first frame. The set of repetitive pattern neighbor candidate vectors may be reduced by sorting the set to eliminate spurious repetitive pattern neighbor candidate vectors. The reduced set may be provided to a second adjacent frame. A method may include acquiring a plurality of sequential video frames having a repetitive pattern content, and determining a set of repetitive pattern neighbor candidate vectors for the repetitive pattern content in a first frame of the sequential video frames. The set of repetitive pattern neighbor candidate vectors may be sorted by determining at least one spurious repetitive pattern neighbor candidate vector.

Abstract: A System-on-Chip (SoC) may include logic blocks connected to each other and to external connections, and a hardware debug infrastructure logic connected to the logic blocks and for performing functional changes to a design layout of the SoC. The hardware debug infrastructure logic may include software re-configurable modules based upon the logic blocks obtained from substituting a mask programmable ECO base cell configured as a functional logic cell for a logic cell in the design layout.

Abstract: The invention concerns a biasing circuit for controlling the current flowing through a differential pair (102, 104) comprising: a first branch comprising a first resistor (306), a first transistor device (308) and a second transistor device (310) coupled in series; a second branch comprising a second resistor (312), a third transistor device (314) and a fourth transistor device (316) coupled in series, a control node of the third transistor device being coupled to a first node (324) between the first resistor and the first transistor device, and a control node of the first transistor device being coupled to a second node (322) between the second resistor and the third transistor device; and an operational amplifier (318) having an output node coupled to control nodes of the second and fourth transistor devices, said output node providing a output signal (Vc) for controlling the current flowing through said differential pair.

Abstract: A lateral phase change memory includes a pair of electrodes separated by an insulating layer. The first electrode is formed in an opening in an insulating layer and is cup-shaped. The first electrode is covered by the insulating layer which is, in turn, covered by the second electrode. As a result, the spacing between the electrodes may be very precisely controlled and limited to very small dimensions. The electrodes are advantageously formed of the same material, prior to formation of the phase change material region.

Abstract: The method is to fabricate a microelectronic device with an integrated antenna. This method may include forming at least a first semiconducting layer on a substrate, forming in at least one zone of the first semiconducting layer of a structure to limit the circulation of current in the zone of the first semiconducting layer, forming a plurality of layers on the semiconducting layer and at least one antenna in the plurality of layers, with the antenna being formed opposite the zone. The antenna may be operable at radio frequencies above 10 GHz, and may have an improved emission efficiency.

Abstract: An apparatus and method for measuring the duty cycle of a clock signal, the apparatus having a first multi-tap delay module, a second multi-tap delay module, and a multi-element detecting module, the input terminal of the first multi-tap delay module and the input terminal of the second multi-tap delay module coupled to an input node IN, the first multi-tap delay module receiving the clock signal and then providing it a first constant incremental delay at each tap, the second multi-tap delay module receiving the same clock signal CLK and then providing it a second constant incremental delay at each tap, and the multi-element detecting module determining the ratio of the number of outputs of the multi-element detecting module in which the sampled clock level is high with respect to the total number of steps covering one complete clock cycle.

Abstract: An analog T switch is disclosed which has high isolation in the off state. The analog T switch can include series-connected NMOS transistors having separate gate control. The gates of the NMOS transistors can be isolated from one another to improve off state isolation of the analog T switch. The analog switch can include series-connected PMOS transistors having separate gate control. The gates of the PMOS transistors can be isolated from one another to improve off state isolation of the analog T switch. The analog T switch can include a substrate voltage control circuit that controls the voltage of the substrate regions in which the PMOS transistors are formed. The substrate voltage control circuit can isolate the substrate regions of the PMOS transistors from one another in the off state to improve off state isolation of the analog T switch.

Abstract: An integrated circuit includes input circuitry for receiving a radio frequency digital signal, output circuitry capable of delivering a radio frequency analog signal, and a processing stage coupled between the input circuitry and the output circuitry and including several processing channels in parallel. Each processing channel may include a voltage switching block the input of which is coupled to the input circuitry and a transmission line substantially of the quarter-wave type at the frequency of the radio frequency analog signal coupled in series between the output of the voltage switching block and the output circuitry.

Abstract: Controlling a resonant switching system, which includes a first switch and a second switch in a half-bridge configuration for driving a resonant load. A corresponding control system includes command means for switching on and switching off the switches alternatively according to a working frequency of the switching system. The control system includes detection means for detecting a zeroing of a working current being supplied by the switching system to the resonant load in a temporal observation window; the observation window follows each switching off of at least one of the switches, and has a length equal to a fraction of a to working period of the switching system. Correction means are then provided for modifying the working frequency in response to each detection of the zeroing in the observation window.

Abstract: A control device for regulating the constant output current of a flyback converter, the control device adapted to control the on time period and the off time period of a primary winding switch and including a first circuit adapted to multiply a first signal representative of current flowing through the primary winding and a second signal representative of an input voltage and outputting a signal representative of the multiplication, a second circuit adapted to compare the output signal of the first circuit and a third signal representative of the direct output voltage, the control device determining, on the basis of the output signal of the second circuit, the on time period and the off time period of the switch so that the output signal of the first circuit is equal to the signal representative of the direct output signal to have the output current of the flyback converter constant.

Abstract: A Micro Electro Mechanical Systems resonance device includes a substrate, and an input electrode, connected to an alternating current source having an input frequency. The device also includes an output electrode, and at least one anchoring structure, connected to the substrate. The device further includes a vibratile structure connected to an anchoring structure by at least one junction, having a natural acoustic resonant frequency. The vibration under the effect of the input electrode, when it is powered, generates, on the output electrode, an alternating current wherein the output frequency is equal to the natural frequency. The vibratile structure and/or the anchoring structure includes a periodic structure. The periodic structure includes at least first and second zones different from each other, and corresponding respectively to first and second acoustic propagation properties.

Abstract: Nanosized filamentary carbon structures (CNTs) nucleating over a catalyzed surface may be grown in an up-right direction reaching a second surface, spaced from the first surface, without the need of applying any external voltage source bias. The growth process may be inherently self-stopping, upon reaching a significant population of grown CNTs on the second surface. A gap between the two surfaces may be defined for CNT devices being simultaneously fabricated by common integrated circuit integration techniques. The process includes finding that for separation gaps of up to a hundred or more nanometers, a difference between the respective work functions of the materials delimiting the gap space, for example, different metallic materials or a doped semiconductor of different dopant concentration or type, may produce an electric field intensity orienting the growth of nucleated CNTs from the surface of one of the materials toward the surface of the other material.

Abstract: Multiple virtual MAC addresses may be added to WGA devices that may have different traffic streams to another device that requires different services, thus creating distinct MAC and device level implications. Beamforming training can be done at the device level for all virtual MAC addresses. Wakeup, doze, and ATIM power save can be done at the device level depending on the frames received. Authentication, deauthentication, association, and deassociation can be done variously at both levels. Further MSDUs can be aggregated for the multiple MAC addresses.

Abstract: Aspects of the invention are directed towards an apparatus and method for detecting conventional and exotic cadences in video sequences. The cadence detector includes a motion auto-correlation unit using the inter-frame/field motion information to detect the cadence and a motion cross-correlation unit using the inter-frame/field motion information and the detected cadence to determine the cadence phase. The cadence detector also may include a reset signal generator to generate a reset signal to control the motion auto-correlation unit and the motion cross-correlation unit. The exotic cadence detector is robust and may support many cadences with reduced cadence detection latency as compared to the prior art.