Abstract: A controller includes a clock control unit configured to provide a first output to test circuitry and a bypass unit configured to provide a second output to a further controller. The controller is configured to cause the bypass unit to output the second output and to optionally cause the clock control unit to output the first output.

Abstract: A mesa-type bidirectional vertical power component, including a substrate of a first conductivity type; a layer of the second conductivity type on each side of the substrate; first regions of the first conductivity type in each of the layers of the second conductivity type; and, at the periphery of each of its surfaces, two successive grooves, the internal groove crossing the layers of the second conductivity type, second doped regions of the first conductivity type being formed under the surface of the external grooves and having the same doping profile as the first regions.

Abstract: Test circuits and methods for detecting faults in integrated devices are disclosed. In an embodiment, a circuit may include an input node configured to receive a test signal, and a transition circuit configured to generate a transit on at least one voltage level indicator pin dependent on the test signal. The circuit may also include a data capture circuit configured to capture the output of the at least one voltage level indicator pin to test for stuck-at faults. In another embodiment, a method may include receiving a test signal, generating a transit on at least one voltage level indicator pin dependent on the test signal, and capturing the output of the at least one voltage level indicator pin to test for stuck-at faults.

Abstract: A keyboard may include a plurality of optical keys. Each optical key may include an optical module and an interaction surface. The optical key may be configured to be activated based on movement of an object on or adjacent the interaction surface. Each movement may produce a different output from the optical module to thereby generate a predetermined input for a device.

Abstract: Methods and apparatuses for detection and reduction of wind noise in audio devices are disclosed. In an embodiment, a method includes acquiring and transforming the audio signals. Correlations from the transformed audio signals are computed. A cross correlation index is compared to a predetermined value to determine if a wind noise spectral content is present. In another embodiment, an apparatus includes an audio processing unit to receive non-decomposed audio signals, and an audio decomposition unit to receive the non-decomposed audio signals and to generate decomposed audio signals. A wind noise spectrum estimation unit receives non-decomposed audio signals and decomposed audio signals and identifies wind noise spectral components in at least one of the non-decomposed and decomposed audio signals. A wind noise spectrum reduction unit receives the wind noise spectral components and removes the wind noise spectral components from at least one of the non-decomposed and the decomposed audio signals.

Abstract: A clock circuit includes a frequency or phase comparator for receiving a reference clock signal, an LC VCO coupled to the comparator, a feedback divider coupled between the LC VCO and the comparator, a clock distribution chain coupled to the feedback divider and the first VCO, and a DLL or injection-locked ring-VCO coupled to the clock distribution chain for providing a plurality of phased output clock signals.

Abstract: A method for reading a magnetic-field sensor provided with at least one first magnetoresistive element envisages generation of an output signal, indicative of a magnetic field, as a function of a detection signal supplied by the magnetic-field sensor. The reading method envisages: determining an offset signal present in the output signal; generating at least one compensation quantity as a function of the offset signal; and feeding back the compensation quantity at input to the reading stage so as to apply a corrective factor at input to the reading stage as a function of the compensation quantity, such as to reduce the value of the offset signal below a given threshold.

Abstract: An appropriate motion vector to assign to a pixel in a digital video frame is performed by a comparison of motion vectors of particular surrounding pixels. Direction of at least one of color transition or color brightness transition in the digital video frame is detected to detect direction of object boundaries in the digital video frame. The particular surrounding pixels are selected and grouped (filtered) according to the detected object boundary direction at each pixel. A comparison of the motion vectors of the surrounding pixels then provides information on which group of pixels to assign a current pixel being processed based in part on how close the motion vectors of the surrounding groups match a group pixels to which the pixel being processed belongs.

Abstract: Lens alignment apparatuses, methods and optical devices are disclosed. In accordance with various embodiments, a lens alignment apparatus may include at least one lens element positioned in a lens body. A lens alignment interface coupled to the lens element may be configured to permit the lens element to be angularly deflected relative to an axis of symmetry of the lens body. In other embodiments, a method of improving the resolution of an optical device may include translating a lens along an optical axis to maximize resolution at a first location, and determining a resolution in a second location in the imaging plane. The resolution in the second location may be improved by angularly deflecting the lens, and the position of the lens may then be fixed.

Abstract: A management apparatus is described of a rotating motor and a load during power loss; the apparatus comprises a first switching circuit coupled with the rotating motor and a controller of said first switching circuit. The controller is configured to drive the first switching circuit so as to convert a back-electromotive force voltage developed in the rotating motor into a power supply voltage for the load. The first switching circuit is driven in accordance with a first duty cycle. The apparatus comprises a second switching circuit coupled with the load and driven in accordance with a second duty cycle. The controller is configured to vary said first and said second duty cycles to keep the power supply voltage for the load above or equal to a threshold voltage.

Abstract: A method is provided for reading a captured image, with the captured image comprising at least first and second parts and a border area positioned between the first and second parts. Converted pixels are obtained by applying digital-to-analog conversion to the pixels in the captured image, and the converted pixels corresponding to the border area of the captured image are stored in a buffer. A first set of processed pixels is obtained by applying image processing to the converted pixels corresponding to the first part of the image and to the converted pixels stored in the buffer, and a second set of processed pixels is obtained by applying image processing to the converted pixels corresponding to the second part of the image and to the converted pixels stored in the buffer. A processed image is provided by combining the first and second sets of processed pixels. Also provided is a processing device for reading a captured image.

Abstract: A control circuit for a full-bridge-stage to drive an electric load includes PWM generation circuitry for generating first and second PWM signals so that a difference between duty-cycles of the PWM signals represents an amplitude of a drive current. A logic XOR gate is input with the first and second PWM signals and generates a logic XOR signal. A logic sampling circuit generates a logic driving command of a half-bridge stage, a logic value of which corresponds to a sign of the drive current, by sampling one of the first and second PWM signals based upon active switching edges of the logic XOR signal. A second XOR gate generates a third PWM driving signal of the other half-bridge of the full-bridge stage, a duty-cycle of which corresponds to the amplitude of the drive current.

Abstract: A cache memory comprises a first set of storage locations for holding syllables and addressable by a first group of addresses; a second set of storage locations for holding syllables and addressable by a second group of addresses; addressing circuitry operable to provide in each addressing cycle a pair of addresses comprising one from the first group and one from the second group, thereby accessing a plurality of syllables from each set of storage locations; and selection circuitry operable to select from said plurality of syllables to output to a processor lane based on whether a required syllable is addressable by an address in the first or second group.

Abstract: An electronic synchronous/asynchronous transceiver device for power line communication networks is integrated into a single chip and operates from a single supply voltage. The transceiver device includes: at least an internal register that is programmable through a synchronous serial interface; at least a line driver for a two-way network communication over power lines implemented by a single ended power amplifier with direct accessible input and output lines that is part of a tunable active filter for the transmission path; and at least a couple of linear regulators for powering with different voltage levels different kind of external controllers linked to the transceiver device.

Abstract: The present disclosure relates to a method for enabling a virtual processing unit to access a peripheral unit, the virtual processing unit being implemented by a physical processing unit connected to the peripheral unit, the method comprising a step of transmitting to the peripheral unit a request sent by the virtual processing unit to access a service provided by the peripheral unit, the access request comprising at least one parameter and an identifier of the virtual unit, the method comprising steps, executed by the peripheral unit after receiving an access request, of allocating a set of registers to the virtual unit identifier received, storing the parameter received in the register set allocated, and when the peripheral unit is available for processing a request, selecting one of the register sets, and triggering a process in the peripheral unit from the parameters stored in the selected register set.

Abstract: An IO buffer module optimized for a wide range of drive levels both in terms of area and performance that includes an IO cell module and at least one IO adder module operatively coupled to said IO cell module for enabling the IO buffer module for the wide range of drive levels. The IO adder module can be added with the IO cell module in a number of different combinations for providing the wide range of drive levels, and the IO buffer module can provide drive solutions from 1 mA to 10 mA or higher, in steps of 0.5 mA drive level.

Abstract: The embodiments of the present disclosure teach overlaying videos on a display device. The technique involves one or more buffers at input such as a first buffer (Primary Buffer) and an overlay buffer, a blitting module, a second buffer(Frame Buffer), and a display screen. The first buffer provides a first image data to the blitting module and the overlay buffer provides a second image data to the blitting module. The embodiments of the present disclosure demonstrate overlaying the second image on the first image with enhanced configurable functionality (like stretching, clipping, color keying, Alpha Blending and Raster Operation) if required, without modifying the Primary Buffer without the need of any overlay support in hardware.

Abstract: A method for manufacturing a strained channel MOS transistor including the steps of: forming, at the surface of a semiconductor substrate, a MOS transistor comprising source and drain regions and an insulated sacrificial gate which partly extends over insulation areas surrounding the transistor; forming a layer of a dielectric material having its upper surface level with the upper surface of the sacrificial gate; removing the sacrificial gate; etching at least an upper portion of the exposed insulation areas to form trenches therein; filling the trenches with a material capable of applying a strain to the substrate; and forming, in the space left free by the sacrificial gate, an insulated MOS transistor gate.

Abstract: A camera module includes a single lens system, a sensor and an image enhancer. The image enhancer is operable to enhance a single image captured by the sensor via the single lens system. The image enhancer performs opto-algorithmic processing to extend the depth of field of the single lens system, a mapping to derive a depth map from the captured single image; and image processing to calculate suitable offsets from the depth map as is required to produce a 3-dimensional image. The calculated offsets are applied to appropriate image channels so as to obtain the 3-dimensional image from the single image capture.

Abstract: A directional anti-aliasing filter circuit includes an input node and an output node, a directional anti-aliasing filter having an input coupled to the input node, an adaptive gain control having an input coupled to an output of the directional anti-aliasing filter, a summer having a first input coupled to an output of the adaptive gain control, a second input coupled to the input node, and an output coupled to the output node, a texture detector for providing a texture adjust signal to the directional anti-aliasing filter and a texture adaptive gain signal to the adaptive gain control, an edge detector for providing an edge direction signal to the directional anti-aliasing filter, and a corner detector for providing a corner adaptive gain signal to the adaptive gain control.