Patents Assigned to Sumco Corporation
  • Publication number: 20220056613
    Abstract: A vapor deposition device is provided that can make uniform a CVD film thickness at a circumferential edge of a wafer. A carrier is formed in an endless ring shape having a bottom surface that rests on a top surface of a susceptor, a top surface touching and supporting an outer edge of a reverse face of a wafer, an outer circumferential wall surface, and an inner circumferential wall surface, and the carrier is also configured with a structure or shape in a circumferential direction of the top surface that has a correspondence relationship to a crystal orientation in the circumferential direction of the wafer, and a before-treatment wafer is mounted on the carrier such that the crystal orientation in the circumferential direction of the before-treatment wafer and the structure or shape in the circumferential direction have a correspondence relationship.
    Type: Application
    Filed: November 5, 2019
    Publication date: February 24, 2022
    Applicant: SUMCO CORPORATION
    Inventors: Naoyuki WADA, Yu MINAMIDE
  • Publication number: 20220056581
    Abstract: A vapor deposition device is provided that can ameliorate or improve the LPD quality. A vapor deposition device includes a first holder that supports a carrier at a topmost-level and a second holder that supports the carrier under the first holder in a load-lock chamber, and a second robot mounts a before-treatment wafer extracted from a wafer storage container on the carrier standing by at the first holder in the load-lock chamber.
    Type: Application
    Filed: November 5, 2019
    Publication date: February 24, 2022
    Applicant: SUMCO CORPORATION
    Inventors: Naoyuki WADA, Yu MINAMIDE
  • Patent number: 11245014
    Abstract: Provided is a method of producing an epitaxial silicon wafer having high gettering capability resulting in even more reduced white spot defects in a back-illuminated solid-state imaging device. The method includes: a first step of irradiating a surface of a silicon wafer with cluster ions of CnHm (n=1 or 2, m=1, 2, 3, 4, or 5) generated using a Bernas ion source or an IHC ion source, thereby forming, in the silicon wafer, a modifying layer containing, as a solid solution, carbon and hydrogen that are constituent elements of the cluster ions; and a subsequent second step of forming a silicon epitaxial layer on the surface. In the first step, peaks of concentration profiles of carbon and hydrogen in the depth direction of the modifying layer are made to lie in a range of more than 150 nm and 2000 nm or less from the surface.
    Type: Grant
    Filed: August 24, 2018
    Date of Patent: February 8, 2022
    Assignee: SUMCO CORPORATION
    Inventors: Takeshi Kadono, Kazunari Kurita
  • Patent number: 11242617
    Abstract: A silicon single crystal production method includes pulling up and growing a silicon single crystal from silicon melt containing red phosphorus as a dopant by Czochralski process. The silicon single crystal is intended for a 200-mm-diameter wafer. The silicon single crystal includes a straight body with a diameter in a range from 201 mm to 230 mm. The straight body includes a straight-body start portion with an electrical resistivity in a range from 0.8 m?cm to 1.2 m?cm. A crystal rotation speed of the silicon single crystal is controlled to fall within a range from 17 rpm to 40 rpm for at least part of a shoulder-formation step for the silicon single crystal.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: February 8, 2022
    Assignee: SUMCO CORPORATION
    Inventors: Koichi Maegawa, Yasuhito Narushima, Yasufumi Kawakami, Fukuo Ogawa
  • Publication number: 20220034829
    Abstract: A thermal conductivity estimation method includes: measuring temperature distribution of a measurement sample surface in a steady state by partially heating the measurement sample under predetermined heating conditions; calculating temperature distribution of a sample model surface by performing a heat-transfer simulation on the sample model of the same shape as the measurement sample for a plurality of combinations of provisional thermal conductivities and heating conditions; making a regression model, whose input is temperature distribution of the measurement sample surface and whose output is a thermal conductivity of the measurement sample, by a machine learning technique using training data in a form of a calculation result of the plurality of combinations and the temperature distribution obtained from the plurality of combinations; and estimating the thermal conductivity of the measurement sample by inputting a measurement result of the temperature distribution of the measurement sample surface into the
    Type: Application
    Filed: November 18, 2019
    Publication date: February 3, 2022
    Applicant: SUMCO CORPORATION
    Inventors: Ryusuke YOKOYAMA, Toshiyuki FUJIWARA, Yusuke HIGUCHI, Toru UJIHARA
  • Publication number: 20220028969
    Abstract: To provide a silicon epitaxial wafer production method and a silicon epitaxial wafer in which the DIC defects can be suppressed, a silicon epitaxial wafer production method is provided, in which an epitaxial layer is grown in a vapor phase on a principal plane of a silicon single crystal wafer. The principal plane is a {110} plane or a plane having an off-angle of less than 1 degree from the {110} plane. The silicon epitaxial wafer production method includes setting a temperature of the silicon single crystal wafer to 1140° C. to 1165° C. and growing the epitaxial layer in the vapor phase at a growth rate of 0.5 ?m/min to 1.7 ?m/min.
    Type: Application
    Filed: August 5, 2019
    Publication date: January 27, 2022
    Applicant: SUMCO CORPORATION
    Inventors: Masayuki ISHIBASHI, Midori YOSHIDA, Daisuke MARUOKA
  • Publication number: 20220020585
    Abstract: To provide a silicon epitaxial wafer production method and a silicon epitaxial wafer in which the DIC defects can be suppressed, a silicon epitaxial wafer production method is provided, in which an epitaxial layer is grown in a vapor phase on a principal plane of a silicon single crystal wafer. The principal plane is a {110} plane or a plane having an off-angle of less than 1 degree from the {110} plane. The silicon epitaxial wafer production method includes setting a temperature of the silicon single crystal wafer to 1100° C. to 1135° C. and growing the epitaxial layer in the vapor phase at a growth rate of 2.0 ?m/min to 3.0 ?m/min.
    Type: Application
    Filed: August 5, 2019
    Publication date: January 20, 2022
    Applicant: SUMCO CORPORATION
    Inventors: Masayuki ISHIBASHI, Midori YOSHIDA, Daisuke MARUOKA
  • Patent number: 11214863
    Abstract: A method of controlling contamination of a vapor deposition apparatus includes: a wafer loading step of loading a wafer for contamination evaluation into a chamber of the vapor deposition apparatus; a heat treatment step of heat treating the wafer for contamination evaluation at a heat treatment temperature of 1190° C. or more at a hydrogen flow rate of 30 slm or less; a wafer unloading step of unloading the wafer for contamination evaluation from the inside of the chamber; and a wafer contamination evaluation step of evaluating a level of metal contamination of the wafer for contamination evaluation. In a method of producing an epitaxial wafer, epitaxial growth is performed using a vapor deposition apparatus whose contamination is controlled by the contamination controlling method.
    Type: Grant
    Filed: December 4, 2018
    Date of Patent: January 4, 2022
    Assignee: SUMCO CORPORATION
    Inventor: Shota Kinose
  • Publication number: 20210404087
    Abstract: A semiconductor wafer including a single crystal doped with a dopant, wherein a resistivity of the wafer is 0.7 m?-cm or less, and wherein a striation height of the wafer is 6 mm or more. The resistivity of the wafer may be 0.8 m?-cm or less, and the striation height may be 13 mm or more. The resistivity of the wafer may be 0.7 m?-cm or less, and the striation may be 22 mm or more. Example features relate to a method of making a semiconductor wafer that includes adding a dopant to a silicon melt, rotationally pulling a crystal from the silicon melt, and applying a magnetic field of 3000 G or more such that the semiconductor wafer has a resistivity that is equal to or less than 0.8 m?-cm and a striation height that is equal to or more than 13 mm.
    Type: Application
    Filed: June 29, 2020
    Publication date: December 30, 2021
    Applicant: SUMCO CORPORATION
    Inventors: Yasuhito NARUSHIMA, Masayuki UTO
  • Patent number: 11208718
    Abstract: An epitaxial growth device includes; a chamber; a susceptor; a supporting shaft, having a main column located coaxially with the center of the susceptor and supporting arms; and a lift pin, at least the surface layer region of the lift pin is made of a material having a hardness lower than the susceptor, the lift pin has a straight trunk part upper region configured to pass through the through-hole of the susceptor and having a surface roughness of from not less than 0.1 ?m to not more than 0.3 ?m, and the lift pin has a straight trunk part lower region configured to pass through the through-hole of the supporting arm and having a surface roughness of from not less than 1 ?m to not more than 10 ?m.
    Type: Grant
    Filed: April 25, 2016
    Date of Patent: December 28, 2021
    Assignee: SUMCO CORPORATION
    Inventor: Masaya Sakurai
  • Patent number: 11211285
    Abstract: In a method of producing a bonded wafer, the amount of depression of the polishing cloth is 50 ?m to 90 ?m, and the surface hardness (ASKER C) of the polishing cloth is 50 to 60. In the bonded wafer, the polycrystalline silicon layer has a thickness variation ?t of 5% or less, and the support substrate wafer has a GBIR of 0.2 ?m or less and an SFQR of 0.06 ?m or less after the polycrystalline silicon layer is polished.
    Type: Grant
    Filed: January 8, 2019
    Date of Patent: December 28, 2021
    Assignee: SUMCO CORPORATION
    Inventors: Youzou Satou, Kazuaki Kozasa
  • Patent number: 11211423
    Abstract: A method of producing a semiconductor epitaxial wafer is provided. The method includes irradiating a surface of a semiconductor wafer with cluster ions to form a modified layer in a surface portion of the semiconductor wafer, in which the modified layer includes a constituent element of the cluster ions in solid solution. The method further includes forming an epitaxial layer on the modified layer of the semiconductor wafer. The irradiating is performed such that a portion of the modified layer in a thickness direction becomes an amorphous layer, and an average depth of an amorphous layer surface from a semiconductor wafer surface-side of the amorphous layer is at least 20 nm from the surface of the semiconductor wafer.
    Type: Grant
    Filed: March 12, 2020
    Date of Patent: December 28, 2021
    Assignee: SUMCO CORPORATION
    Inventor: Ryosuke Okuyama
  • Patent number: 11198161
    Abstract: A cleaning device for cleaning the inside of a monocrystal pulling apparatus includes a main tube part that is capable of being inserted into a pull chamber and a wire cleaning mechanism that is provided at an upper portion of the main tube part and is configured to clean a pulling wire to be inserted into the main tube part. The main tube part includes a continuous extension mechanism that adds together and joins a plurality of joint tube parts in an axial direction and allows the plurality of joint tube parts to be sealed and connected to each other. Accordingly, the cleaning device is configured to efficiently clean the wire by preventing powdery dust from adhering thereto again.
    Type: Grant
    Filed: February 2, 2017
    Date of Patent: December 14, 2021
    Assignee: SUMCO CORPORATION
    Inventor: Kenji Okita
  • Patent number: 11198949
    Abstract: Provided is a method of producing an epitaxial silicon wafer, which is excellent in productivity and prevents the formation of a backside haze in consecutive single-wafer processing epitaxial growth procedures on a plurality of silicon wafers without cleaning a process chamber after each epitaxial growth procedure. The method of producing an epitaxial silicon wafer includes: a step of loading a silicon wafer; a step of forming a silicon epitaxial layer; a step of unloading the silicon wafer; and a cleaning step. The cleaning step is performed before and after repeating a predetermined number of times a series of growth procedures including the silicon wafer loading step, the silicon epitaxial layer formation step, and the silicon wafer unloading step.
    Type: Grant
    Filed: November 20, 2017
    Date of Patent: December 14, 2021
    Assignee: SUMCO CORPORATION
    Inventors: Masayuki Tsuji, Motonori Nakamura
  • Patent number: 11195716
    Abstract: The method of producing a semiconductor epitaxial wafer includes: a first step of irradiating a surface of a semiconductor wafer with cluster ions containing carbon, phosphorus, and hydrogen as constituent elements to form a modified layer that is located in a surface layer portion of the semiconductor wafer and that contains the constituent elements of the cluster ions as a solid solution; and a second step of forming an epitaxial layer on the modified layer of the semiconductor wafer. The ratio y/x of the number y of the phosphorus atoms with respect to the number x of the carbon atoms satisfies 0.5 or more and 2.0 or less, where the number of atoms of carbon, phosphorus, and hydrogen in the cluster ions is expressed by CxPyHz (x, y, and z are integers each equal to or more than 1).
    Type: Grant
    Filed: January 8, 2019
    Date of Patent: December 7, 2021
    Assignee: SUMCO CORPORATION
    Inventor: Ryosuke Okuyama
  • Publication number: 20210375782
    Abstract: A method of producing a silicon wafer includes: a laser mark printing step of printing a laser mark having a plurality of dots on a silicon wafer; an etching step of performing etching on at least a laser-mark printed region in a surface of the silicon wafer; and a polishing step of performing polishing on both surfaces of the silicon wafer having been subjected to the etching step. In the laser mark printing step, each of the plurality of dots is formed by a first step of irradiating a predetermined position on a periphery of the silicon wafer with laser light of a first beam diameter thereby forming a first portion of the dot and a second step of irradiating the predetermined position with laser light of a second beam diameter that is smaller than the first beam diameter thereby forming a second portion of the dot.
    Type: Application
    Filed: September 6, 2019
    Publication date: December 2, 2021
    Applicant: SUMCO Corporation
    Inventor: Yoichiro HIRAKAWA
  • Patent number: 11186921
    Abstract: A method of controlling a convection pattern of a silicon melt includes: acquiring a temperature at a first measurement point not overlapping a rotation center of a quartz crucible on a surface of the silicon melt, the quartz crucible rotating in a magnetic-field-free state; determining that the temperature at the first measurement point periodically changes; and fixing a direction of a convection flow to a single direction in a plane orthogonal with an application direction of a horizontal magnetic field in the silicon melt by starting a drive of a magnetic-field applying portion to apply the horizontal magnetic field to the silicon melt when a temperature change at the first measurement point reaches a predetermined state, and subsequently raising the intensity to 0.2 tesla or more.
    Type: Grant
    Filed: February 27, 2019
    Date of Patent: November 30, 2021
    Assignee: SUMCO CORPORATION
    Inventors: Ryusuke Yokoyama, Wataru Sugimura
  • Publication number: 20210363660
    Abstract: A method of evaluating cleanliness of a member having a silicon carbide surface, the method including bringing the silicon carbide surface into contact with a mixed acid of hydrofluoric acid, hydrochloric acid and nitric acid; concentrating the mixed acid brought into contact with the silicon carbide surface by heating; subjecting a sample solution obtained by diluting a concentrated liquid obtained by the concentration to quantitative analysis of metal components by Inductively Coupled Plasma-Mass Spectrometry; and evaluating cleanliness of the member having a silicon carbide surface on the basis of a quantitative result of metal components obtained by the quantitative analysis.
    Type: Application
    Filed: August 3, 2021
    Publication date: November 25, 2021
    Applicant: SUMCO CORPORATION
    Inventors: Takashi MURAMATSU, Hirokazu KATO
  • Patent number: 11183433
    Abstract: Provided is a method of evaluating a silicon layer, including forming an oxide film on a surface of a silicon layer, performing a charging treatment of charging a surface of the formed oxide film to a negative charge, and measuring a resistivity of the silicon layer that has been subjected to the charging treatment by a van der Pauw method.
    Type: Grant
    Filed: January 18, 2019
    Date of Patent: November 23, 2021
    Assignee: SUMCO CORPORATION
    Inventors: Sayaka Makise, Shuichi Samata, Noritomo Mitsugi, Sumio Miyazaki
  • Publication number: 20210358755
    Abstract: An epitaxial wafer that includes a silicon wafer and an epitaxial layer on the silicon wafer. The silicon wafer contains hydrogen that has a concentration profile including a first peak and a second peak. A hydrogen peak concentration of the first peak and a hydrogen peak concentration of the second peak are each not less than 1×1017 atoms/cm3.
    Type: Application
    Filed: July 28, 2021
    Publication date: November 18, 2021
    Applicant: SUMCO CORPORATION
    Inventor: Ryosuke OKUYAMA