Abstract: A plurality of PCIe switch complexes are interposed between a plurality of I/O devices and a plurality of microprocessor complexes. Each PCIe switching complex comprises a plurality of PCIe switches wherein each switch possesses at least one non-transparent port. The non-transparent port is used to cross-couple each PCIe switch creating an active matrix of paths between the HBAs associated with each I/O device and each microprocessor. The paths between each HBA (I/O device) and each microprocessor are mapped using a recursive algorithm providing each I/O device with direct memory access to each microprocessor.

Abstract: Determining server capabilities during a discrete time period, or interval, allows for more efficient processing of client requests. Updating a proportional server capability load balancing information encoding at intervals allows a load balancer to handle client requests without the overhead of determining current server capabilities. Decision-making can be reduced to quick selection of one of a group of servers without considering the server's capability, since the server's capability has previously been considered when collecting the load balancing information.

Abstract: In some circumstances a generational garbage collector may be made more efficient by “pre-tenuring” objects or directly allocating new objects in an old generation instead of allocating them in the normal fashion in a young generation. A pre-tenuring decision is made by a two step process. In the first step, during a young-generation collection, an execution frequency is determined for each allocation site and sites with the highest execution frequency are selected as candidate sites. In the second step, during a subsequent young-generation collection, the survival rates are determined for the candidate sites. After this, objects allocated from sites with sufficiently high survival rates are allocated directly in the old generation.

Abstract: A method and apparatus for performing on-chip voltage sampling of a weakly-driven node of a semiconductor device are disclosed. In some embodiments, the node is a floating node or is capacitively-driven. In some embodiments, it is involved in proximity-based communication. Sampling the node may include isolating the signal to be sampled using a source-follower amplifier before passing it to the sampling circuit. Sampling the node may include biasing the node to a desired voltage using a leaky transistor or other biasing circuit. In some embodiments, the biasing circuit may also be used to calibrate the sampler by coupling one or more calibration voltages to the node in place of a biasing voltage and measuring the sampler output. The sampler may be suitable for sub-sampling high frequency signals to produce a time-expanded, lower frequency version of the signals. The output of the sampler may be a current communicated off-chip for testing.

Abstract: A method for providing a secure lockout from executing application programs is provided. An opaque graphical component obscures graphical components for all executing software (applications) programs on a display apparatus and prevents events from reaching the executing application programs.

Abstract: A system for cooling a semiconductor device is disclosed. The system includes a lid encasing the semiconductor device, a first plurality of carbon nanotubes disposed within the lid, and a fluid system configured to pass a fluid through the lid. Furthermore, a second system for cooling a semiconductor device is disclosed. The second system includes a lid, a first plurality of carbon nanotubes disposed within the lid, and a fluid system configured to pass a fluid through the lid. The lid is configured to be mounted over and encase the semiconductor device. Additionally, a method for cooling a semiconductor device is disclosed. The method includes disposing a first plurality of carbon nanotubes within a lid, mounting the lid over the semiconductor device, and passing a fluid through the lid.

Abstract: In computer systems including memory which execute programs of instructions, vtables associated with objects contain pointers which invoke operations to be performed by the program which are related to the objects. The operation invoked may include the step of modifying the pointer such that upon a subsequent reference to the vtable a different operation is invoked.

Abstract: A memory controller, system, and methods are disclosed. The system comprises a memory controller interconnected to a plurality of memory chips. Each memory chip stores data at a plurality of locations. The memory controller performs a sparing transaction comprising reading data from a given location of one or more of the memory chips including a first memory chip, writing the data to a given location of one or more of the memory chips including a second memory chip, wherein during writing, data from the first memory chip is written to the second memory chip, and allowing additional memory transactions directed to the memory chips between the start of reading and the end of writing unless the additional memory transaction is targeted to the given location. In a further embodiment, the sparing transaction comprises correcting errors in the data before writing the data.

Abstract: Selective trace cache invalidation for self-modifying code via memory aging advantageously retains some of the entries in a trace cache even during self-modifying code events. Instructions underlying trace cache entries are monitored for modification in groups, enabling advantageously reduced hardware. Associated with each trace cache entry are translation ages that are determined when the entry is built by sampling current ages of memory blocks underlying the entry. When the entry is accessed and micro-operations therein processed, the translation ages of the accessed entry are compared with the current ages of the memory blocks underlying the accessed entry. If any of the age comparisons fail, then the micro-operations are aborted and the entry is invalidated. When any portion of a memory block is modified, the current age of the modified memory block is incremented. If one of the current ages overflows, then the entire trace cache is flushed.

Abstract: A method and mechanism for controlling threads in a multithreaded multicore processor. A processor includes multiple cores, each of which are capable of executing multiple threads. A control register which is shared by each of the cores is utilized to control the status of the threads in the processing system. In one embodiment, the shared register includes a single bit for each thread in the processor. Depending upon the value written to a bit of the shared register, one of three results may occur with respect to a thread which corresponds to the bit. In one embodiment, writing a “0” to a bit of the shared register will cause a corresponding thread to be Parked. Writing a “1” to a bit of the shared register will cause a corresponding thread to either be UnParked or be Reset. Whether writing a “1” to a bit of the register causes the corresponding thread to be UnParked or Reset depends upon a state of the processor.

Abstract: A system that caches a file within a computer system. During operation, the system monitors accesses to the file, wherein the file is located on a storage device. Next, the system analyzes the monitored accesses to determine an access pattern for the file. The system then uses the determined access pattern to adjust a caching policy for the file.

Abstract: Embodiments of the present invention implement virtual transactional memory using cache line marking. The system starts by executing a starvation-avoiding transaction for a thread. While executing the starvation-avoiding transaction, the system places starvation-avoiding load-marks on cache lines which are loaded from and places starvation-avoiding store-marks on cache lines which are stored to. Next, while swapping a page out of a memory and to a disk during the starvation-avoiding transaction, the system determines if one or more cache lines in the page have a starvation-avoiding load-mark or a starvation-avoiding store-mark. If so, upon swapping the page into the memory from the disk, the system places a starvation-avoiding load-mark on each cache line that had a starvation-avoiding load-mark and places a starvation-avoiding store-mark on each cache line that had a starvation-avoiding store-mark.

Abstract: A fan module for use with fan trays or decks within a computer chassis for forced-air cooling with counter-rotating flow to provide higher static pressure. The fan module may have a conventional side-by-side form factor with a first and second fans supported within first and second housings. The first and second housings are spaced apart and arranged side-by-side. The first fan has a clockwise-rotating blade, and the second fan has a counterclockwise-rotating blade. In the fan module, the first and second fans may be axial fans with the blades rotating about first and second axes that are offset and parallel. In some embodiments, the fan module may have airflow through the first fan in a first direction along the first axis and airflow through the second fan in a second direction along the second axis, with the first and second directions generally matching.

Abstract: A system that includes a network interface for receiving a packets from a network, a classifier operatively connected to the network interface that analyzes each of the packets and determines to which temporary data structure to forward each of packets, wherein the classifier analyzes each packet to determine with which of a plurality of protocols the packet is associated with. Each temporary data structure within the system is configured to receive packets from the classifier, wherein each of the temporary data structures is associated with at least one virtual serialization queue and wherein each of the temporary data structures is configured to store packets associated with at least one of the plurality of protocols. The at least one virtual serialization queue is configured to queue packets from the one of the temporary data structures associated with the at least one virtual serialization queue.

Abstract: One particular implementation takes the form of an apparatus or method for parallelizing a sequential power simulation of an integrated circuit device. The implementation may temporally divide the simulation so that separate time segments of the simulation can be run at the same time, thereby reducing he required time necessary to perform the power simulation. More particularly, a logic simulation may be performed on the integrated circuit and snapshots of the logic devices of the integrated circuit may be taken at a specified period. The separate time segments of the simulation may then be simulated in a parallel manner to simulate power consumption of the integrated circuit. Performing the power simulation on the separate time segments may reduce the required time of a typical power consumption simulation of an integrated circuit.

Abstract: A method for associating sounds with different keypresses, involving receiving an input of a first keypress from a keyboard including a plurality of keys, wherein the keyboard is associated with a computing device, determining whether a key corresponding to the first keypress is one of a plurality of significant elements, wherein the plurality of significant elements is a subset of the plurality of keys, determining a first sound event associated with the key, when the key is one of the plurality of significant elements, and outputting a first sound associated with the first sound event.

Abstract: Methods and apparatuses are presented for controlling a fully buffered dual inline memory module. In one embodiment, the memory module may include at least two memory chips, a buffer coupled to the at least two memory chips (the buffer serially receiving data to be stored in the at least two memory chips), and a heat sink thermally coupled to the at least two memory chips and thermally coupled to the buffer such that heat generated by the buffer is coupled to a first memory chip within the at least two memory chips. The may be configured such that it operates at a higher temperature than the first memory chip and the refresh rate of the first memory chip may be adjusted when the temperature of the first memory chip is outside of a predetermined range.

Abstract: One embodiment of the present invention provides a system that facilitates high-bandwidth communication using a flexible bridge. This system includes a chip with an active face upon which active circuitry and signal pads reside, and a second component with a surface upon which active circuitry and/or signal pads reside. A flexible bridge provides high-bandwidth communication between the active face of the chip and the surface of the second component. This flexible bridge provides a flexible connection that allows the chip to be moved with six degrees of freedom relative to the second component without affecting communication between the chip and the second component. Hence, the flexible bridge allows the chip and the second component to communicate without requiring precise alignment between the chip and the second component.

Abstract: A method for securing a communication between a peer node and an intermediary peer node in a peer-to-peer network comprises the peer node generating a secured communication request to the intermediary peer node. The intermediary peer node authenticates the peer node in response to the secured communication request. The intermediary peer node issues a signed certificate of authority upon successful authentication.

Abstract: A method for optimizing a network stack includes inputting network information into a transport protocol algorithm selector, inputting a first transport protocol algorithm into the transport protocol algorithm selector, analyzing a result of the transport protocol algorithm selector, selecting the first transport protocol algorithm based on the result, receiving a first packet in the network stack, and processing the first packet using the first transport protocol algorithm.