Abstract: According to the invention, a processing core is disclosed that includes a first source register, a number of second operands, a destination register, and a number of arithmetic processors. A bitwise inverter is coupled to at least one of the first number of operands and the second number of operands. The first source register includes a plurality of first operands and the destination register includes a plurality of results. The number of arithmetic processors are respectively coupled to the first operands, second operands and results, wherein each arithmetic processor computes one of a sum and a difference of the first operand and a respective second operand.

Abstract: A method and apparatus for producing an enhanced CRL. In response to a request containing an identifier of the most recently owned CRL stored by the requested, a certificate authority generates a CRL spanning from the most recently owned CRL to the current CRL. This CRL is formatted as a delta CRL and transmitted as a reply to the requester. This has the advantage of not requiring transmission of the full CRL even though more than one generation of CRL has occurred since the most recently owned CRL by the requester.

Abstract: One embodiment of the present invention provides a system that supports directory-based cache coherence in an object-addressed memory hierarchy in a computer system. During operation, the system receives a cache-coherence transaction for a cache line. If the cache line is an object-addressed cache line, the system uses a corresponding object identifier and offset to look up directory information specifying where copies of the object-addressed cache line are located in the caches in the computer system. Next, the system uses the directory information to perform the cache-coherence transaction.

Abstract: Techniques for increasing the performance of virtual machines are disclosed. It can be determined whether a program instruction which is to be executed by the virtual machine is a branch instruction, and whether a basic block of code is present in a code cache. If so, the basic block of code can be executed. The basic block includes code that can be executed for the program instruction. A cache can be used to store the basic block for program instructions that are executed by the virtual machine. The program instruction may be a bytecode and the code cache can be implemented as a native code cache.

Abstract: A transparent proxy server is implemented by directing particular client packets to a proxy server that handles communications between the client and an origin server. When a client sends a packet to an origin server, a router transparently redirects the packet to the proxy server by storing the proxy server address in the destination field and the origin server address in the record route options field. The proxy server sends connection setup requests to the origin server and forwards acknowledgement packets to the client. For other requests, the proxy server determines whether the requested information is stored in the proxy server cache. If so, the information is retrieved from the cache; if not, the information is retrieved from the origin server. All acknowledgement and information packets are sent to the client with the origin server address in the source field, making it appear that the origin server sent the packets.

Abstract: The present invention provides a method and apparatus for capturing system error messages. The method includes accessing information associated with an error. The method further includes identifying a category associated with the error based upon the accessed information and accessing at least one pre-determined attribute in the accessed information based upon the identified category.

Abstract: A computer system comprises first and second computer boards, each having a processor, onboard memory, an onboard bus, e.g. a processor bus, and a bus-to-bus bridge for interconnecting the onboard bus with an external bus; the boards have remote slave drivers, and communication drivers, comprising communication management functions, and forming communication chains or channels between the remote slave drivers and the onboard memories.

Abstract: A system and method for eliminating static initialization overhead by memory space cloning of a master runtime system process is presented. A master runtime system process is executed. One or more static initialization methods are identified. Each static initialization method is uniquely associated with a class provided in a runtime system and specifies a source definition provided as object-oriented program code. At least one static initialization method is executed in a memory space of the master runtime system process. The memory space is cloned as a child runtime system process responsive to a process request. The child runtime system process is executed. In one embodiment, a full garbage collection is performed by promoting objects created during static initialization into the older generation.

Abstract: A method and structure for equipping a cache with information to enable the processor to track and report whether a given speculative access causes prefetches and/or pollutions of the cache. Two types of events are tracked in one of two different ways: first by counting/tracking prefetch operations, either globally or on a per instruction address basis and then by counting/tracking cache pollutions, either globally or on a per instruction address basis.

Abstract: A method and apparatus to determine readiness of a complex instruction for retirement includes decoding a complex instruction into a plurality of helper instructions; executing the plurality of helper instructions using an execution unit; indicating the plurality of helper instructions that are alive using a live instruction register; and maintaining a complex instruction identification for the complex instruction using a complex instruction identification register.

Abstract: A plurality of on-chip temperature sensors are selectively distributed across an integrated circuit. The temperature sensors generate signals indicative of operating temperatures experienced by the portions of the integrated circuit on which the temperature sensors are disposed. Based on the temperatures of the portions of the integrated circuit, operation of particular circuitry of the integrated circuit is dynamically adjusted to counteract the effects of undesirable or unexpected operating temperatures.

Abstract: A computer system is provided having at least one processing resource, at least one power resource and at least one redundant power resource. The at least one processing resource is operable to exploit a greater level of power than is provided by the at least one power resource. The at least one processing resource is configured to exploit power provided by both the at least one power resource and the at least one redundant power resource, at a time when both the at least one power resource and the at least one redundant power resource are both operable to provide power.

Abstract: A fault tolerant computing system is provided comprising two or more processing sets that operate in synchronism with one another. The two processing sets are joined by a bridge, and there is a communications link for each processing set for transmitting data from the processing set to the bridge. Data transmissions are initiated in synchronism with one another from the respective processing sets to the bridge but are then subject to variable delay over the communications link. Accordingly, a buffer is included in the bridge for storing the data transmissions received from the processing sets for long enough to compensate for the variable delay. The data transmissions can then be fed out from the buffer to a comparator that verifies that the data transmissions received from the two or more processing sets properly match each other. Likewise, a buffer is included in each processing set for storing the data transmissions received from the bridge for long enough to compensate for the variable delay.

Abstract: One embodiment of the present invention provides a system that performs voltage sampling over an extended voltage range on a semiconductor chip. During operation, the system receives an input voltage at a node within the semiconductor chip. The system samples the input voltage through a first sampling pathway using NMOS pass gates, which latch the input voltage to produce a first output signal. This first output signal tracks the input voltage from ground up to a cut-off voltage for the nMOS pass gates. The system also samples the input voltage through a second sampling pathway using nMOS pass gates, which latch the input voltage to produce a second output signal. Prior to the NMOS pass gates along the second sampling pathway, the input voltage passes through a source-follower gate, which translates the input voltage down, so that the second output signal tracks the input voltage from a turn-on voltage of the source-follower gate up to Vdd.

Abstract: The present invention relates to managing defunct processes. A parent process that does not collect exit information associated with a child process may leave a defunct child process. A defunct child process is identified. The parent process of the defunct child process is modified. The parent process can be modified by changing an existing thread or instantiating a new thread to collect exit information associated with the child process. Collecting exit information causes the removal of the defunct child process.

Abstract: A thin-client device broadcasts a configuration request message over a network. In response to the configuration request message, the thin-client device receives a configuration response message including a first set of configuration information. The thin-client device determines if the configuration response message includes a second set of configuration information. If the configuration response message does not include the second set of configuration information, the thin-client device broadcasts a status message over a network. In response to the status message, the thin-client device receives a status response message with the second set of configuration information.

Abstract: A method for precognitive fetching, involving receiving an original request, performing pre-fetching analysis using the original request to obtain a pre-fetch request, forwarding the pre-fetch request to a storage subsystem, and receiving a response to the pre-fetch request from the storage subsystem.

Abstract: A computer system includes a system memory and a plurality of active devices configured to access data associated with the system memory through an address network and a data network. Each of the active devices may be configured to cache data, and may include a promise array. Transitions in ownership of the given block may occur at a different time than the time at which the access right to the given block is changed. The promise array of an active device is provided to store information identifying an unreceived data packet to be conveyed to another device in response to a pending transaction to a cache block for which the active device is an owner. Each active device may be configured to have at most one outstanding transaction for each cache block.

Abstract: A method and system are provided for performing automated management on a system. The method includes providing a fault tree representation of the system. The fault tree specifies propagations of errors generated in the system by problems to produce error reports. The method further includes receiving one or more error reports which are analyzed using the fault tree representation to determine one or more suspected problems. The suspected problems represent those problems that could have generated errors to produce the received error reports compatible with the propagations in the fault tree. The method further includes deconfiguring or reconfiguring one or more components in the system in response to the determination of the suspected problems.

Abstract: A system for automatically encrypting and decrypting data packet sent from a source host to a destination host across a public internetwork. A tunnelling bridge is positioned at each network, and intercepts all packets transmitted to or from its associated network. The tunnelling bridge includes tables indicated pairs of hosts or pairs of networks between which packets should be encrypted. When a packet is transmitted from a first host, the tunnelling bridge of that host's network intercepts the packet, and determines from its header information whether packets from that host that are directed to the specified destination host should be encrypted; or, alternatively, whether packets from the source host's network that are directed to the destination host's network should be encrypted.