Patents Assigned to Sun Microsystems
  • Patent number: 7117342
    Abstract: A processor executes an instruction set including instructions in which a register specifier is implicitly derived, based on another register specifier. One technique for implicitly deriving a register specifier is to add or subtract one from a specifically-defined register specifier. Implicit derivation of a register specifier is selectively implemented for some opcodes. A decoder decodes instructions that use implicitly-derived register specifiers and reads the explicitly-defined register. The decoder generates pointers both to the explicitly-defined register and to the implicitly-derived register. In other embodiments, a pointer to registers within a register file includes an additional bit indicating that a register read is accompanied by a read of an implicitly-derived register.
    Type: Grant
    Filed: December 3, 1998
    Date of Patent: October 3, 2006
    Assignee: Sun Microsystems, Inc.
    Inventors: Marc Tremblay, William Joy
  • Patent number: 7117312
    Abstract: A mechanism for filtering snoop requests to a cache memory includes, in one embodiment, a first storage that may store a first set of corresponding snoop filter indications. The mechanism also includes a second storage that may store a second set of corresponding snoop filter indications. Further, the mechanism includes a cache controller configured to receive a transaction request including an address. The cache controller generates a first index value for accessing the first storage by performing a first hash function on the address. In addition, the cache controller generates a second index value for accessing the second storage by performing a second hash function on the address. The cache controller may further selectively generate a snoop operation to the cache memory for the transaction request dependent upon a corresponding snoop filter indication stored in each of the first storage and the second storage that corresponds to the address.
    Type: Grant
    Filed: April 9, 2004
    Date of Patent: October 3, 2006
    Assignee: Sun Microsystems, Inc.
    Inventor: Robert E. Cypher
  • Patent number: 7117489
    Abstract: Techniques for customization of JAVA runtime environments are disclosed. The techniques can be used to provide JAVA runtime environments that are specifically tailored for various JAVA applications. Accordingly, for a particular JAVA application, an optimized runtime environment can be created. One or more optional attributes which represent the desired runtime customizations are generated. As will be appreciated, the optional attributes can be generated in the attribute table in the class file. The optional attributes can then be parsed and appropriate features can be loaded into the virtual machine. In this way, JAVA runtime environments can be customized based on a particular JAVA application requirement. Moreover, customizations can be automated using a runtime performance manager that interacts with various other components that operate to first generate and then load optional attributes into the JAVA runtime environment.
    Type: Grant
    Filed: June 20, 2001
    Date of Patent: October 3, 2006
    Assignee: Sun Microsystems, Inc.
    Inventors: David Wallman, Stepan Sokolov
  • Patent number: 7115817
    Abstract: An electrical assembly comprising a circuit board an electrical device, and a heat dissipation device. The electrical device is capable of emitting thermal energy and electromagnetic interference (EMI). The electrical device is secured to the circuit board. The heat dissipation device is secured to the circuit board and is in thermal communication with the electrical device. The heat dissipation device also includes a continuous EMI fence and a plurality of fins disposed in a matrix orientation. The fins are spaced from one another to allow for efficient heat dissipation and have a substantially square cross-sectional shape.
    Type: Grant
    Filed: September 18, 2002
    Date of Patent: October 3, 2006
    Assignee: Sun Microsystems, Inc.
    Inventors: Thomas E. Stewart, Steven J. Furuta
  • Patent number: 7117267
    Abstract: A system and method for providing HTTP tunnel connections between entities such as clients and servers in a messaging system is described. An HTTP tunnel connection layer is described that may be used to provide reliable, full duplex virtual connections between entities (e.g. clients and brokers) in a distributed application environment using a messaging system. Also described is a novel HTTP tunneling protocol that may be used by the HTTP tunnel connection layer. The HTTP tunnel connection layer may be used by clients to access messaging servers through proxy servers and firewalls, thus expanding the scope of from where clients can access brokers. Using this layer, brokers as well as clients may initiate messaging system messages. This layer may also provide guaranteed data delivery with correct sequencing even in case of a failure on the network. This layer may also provide end-to-end flow control.
    Type: Grant
    Filed: June 28, 2001
    Date of Patent: October 3, 2006
    Assignee: Sun Microsystems, Inc.
    Inventor: Shailesh S. Bavadekar
  • Patent number: 7117360
    Abstract: A method and apparatus for generating a CRL with a last_changed extension. When sequential CRLs are generated there is the potential that there will be no changes in the data associated with the CRL. In this case a recipient of the new CRL may needlessly perform processing on the new CRL. A CRL consistent with embodiments of the present invention provides an extension to specify the CRL number of the last_changed CRL. This provides the recipient with information to determine whether the new CRL should be processed or the existing data is up to date.
    Type: Grant
    Filed: July 9, 2001
    Date of Patent: October 3, 2006
    Assignee: Sun Microsystems, Inc.
    Inventor: Michelle Zhao
  • Patent number: 7117502
    Abstract: A simple and therefore highly usable non-blocking implementations of linked-lists can be provided using read, write, and CAS operations. Several realizations of linked-list based data-structures are described, which are non-blocking, linearizable, and exhibit disjoint-access for most operations. In other words, the realizations are non-blocking and linearizable while maintaining the property that operations on disjoint parts of the list do not interact, effectively lowering contention and increasing concurrency. We implement three exemplary data structures: sets, multi-sets, and ordered-sets. The exemplary implementations support insert, remove, and find operations, with natural semantics. An ordered-set implementation supports an additional removeGE operation.
    Type: Grant
    Filed: November 10, 2000
    Date of Patent: October 3, 2006
    Assignee: Sun Microsystems, Inc.
    Inventor: Timothy L. Harris
  • Patent number: 7117202
    Abstract: A system for conducting a computer based search that includes a bidding bulletin board to post a user search query from a user, an agent that submits a bid to the bidding bulletin board in response to the query, where the agent is associated with a search result, and a display server to display the search result if the bidding bulletin board accepts the bid, where an amount bid is determined by behavioral rules for the agent. Also, a method that includes the steps of posting a user search query from a user on a bidding bulletin board, receiving a bid from an agent at the bidding bulletin board in response to the query, where the agent is associated with a search result, and displaying the search result if the bulletin board accepts the bid, where the amount bid is determined by behavioral rules for the agent.
    Type: Grant
    Filed: June 30, 2003
    Date of Patent: October 3, 2006
    Assignee: Sun Microsystems, Inc.
    Inventor: Douglas A. Willoughby
  • Patent number: 7116126
    Abstract: A method of transmitting adjacent signals is disclosed. Sensing is performed on signals in the group and adjacent signals are either switched or delayed if the adjacent signals are switching at the same time. The method is used in networks where coupling and capacitance effects are possible.
    Type: Grant
    Filed: October 16, 2001
    Date of Patent: October 3, 2006
    Assignee: Sun Microsystems, Inc.
    Inventors: Nayon Tomsio, Harsh D. Sharma
  • Patent number: 7117285
    Abstract: A method and system for efficiently directing interrupts is disclosed. In a computer system having multiple processors, a computer implemented method, upon detecting an interrupt directed to one of the processors, determines a policy for efficiently handling the interrupt. Upon invoking the policy, the interrupt is redirected according thereto to a second processor for handling. The policies include an I/O affinity policy, a local memory policy, and a reduced I/O intension policy. In a multiple processor environment, a computer based system efficiently handles an interrupt directed to one of the processors. The system includes an interrupt dispatching module for redirecting the interrupt from that processor to another processor, where the interrupt is handled. The system also includes an interrupt redirection policy module associated with the interrupt dispatching module. The policy module provides a policy for controlling interrupt redirection, which promotes efficient operation.
    Type: Grant
    Filed: August 29, 2003
    Date of Patent: October 3, 2006
    Assignee: Sun Microsystems, Inc.
    Inventor: Eiji Ota
  • Patent number: 7117486
    Abstract: The present invention provides an integrated migration environment which assists in migration of software systems. The invention further provides an object oriented framework through which the tool can be extended to handle additional languages and platforms. A system and method is provided for the identification of migration issues and subsequent modification of the software system. The system and method can be deployed over the web for quick installation and is executable on multiple platforms. The invention provides a means to migrate software systems from any source platform to any target platform.
    Type: Grant
    Filed: April 25, 2003
    Date of Patent: October 3, 2006
    Assignee: Sun Microsystems, Inc.
    Inventors: Wai Ming Wong, Sandeep Kamat
  • Patent number: 7117304
    Abstract: Embodiments of the present invention include a method for determining a file system layout on a disk. The method includes providing a default file system layout comprising a root partition, a swap partition and a plurality of unassigned partitions. The method further includes assigning a size for each of the partitions, sorting the partitions by size from largest to smallest and identifying available blocks on the disk for the unassigned partitions. The method also includes assigning locations on the disk for the partitions from the largest to the smallest wherein the partitions are filled in the available blocks from end to beginning.
    Type: Grant
    Filed: July 23, 2003
    Date of Patent: October 3, 2006
    Assignee: Sun Microsystems, Inc.
    Inventor: Susan Sohn
  • Patent number: 7117287
    Abstract: An apparatus and method for maintaining a circular FIFO (first-in, first-out) queue in an I/O (input-output) subsystem of a computer system such as a server, workstation, or storage machine. The queue is coupled to a bypass circuit, used to provide access to data items out of the order in which they were stored in the queue, thus bypassing the latency inherent in retrieving the items from the queue. Control logic maintains write and read pointers indicating locations in the queue for writing and reading data items. The write pointer is incremented upon every data event to the queue, thereby maintaining a history of data that has been written to the queue, which is useful for diagnostic purposes. A history flag is maintained to indicate whether the write pointer has wrapped around the addresses in the queue, indicating whether all data items in the queue are valid for diagnostic purposes.
    Type: Grant
    Filed: May 30, 2003
    Date of Patent: October 3, 2006
    Assignee: Sun Microsystems, Inc.
    Inventor: Brian Smith
  • Patent number: 7117359
    Abstract: A security architecture has been developed in which a single sign-on is provided for multiple information resources. Rather than specifying a single authentication scheme for all information resources, the security architecture associates trust-level requirements with information resources. Authentication schemes (e.g., those based on passwords, certificates, biometric techniques, smart cards, etc.) are employed depending on the trust-level requirement(s) of an information resource (or information resources) to be accessed. Once credentials have been obtained for an entity and the entity has been authenticated to a given trust level, access is granted, without the need for further credentials and authentication, to information resources for which the authenticated trust level is sufficient. In addition, an entity can be allocated a new session and associated default credential if the entity's access request indicates an invalid session token or does not indicate a token.
    Type: Grant
    Filed: September 12, 2005
    Date of Patent: October 3, 2006
    Assignee: Sun Microsystems, Inc.
    Inventors: David L. Wood, Paul Weschler, Derk Norton, Chris Ferris, Yvonne Wilson, William R. Soley
  • Patent number: 7117422
    Abstract: Provided are a method, system, and an article of manufacture for detecting errors while accessing a storage device. A host system writes an identical initialization pattern into each block of a plurality of blocks while formatting the storage device. Each block of the plurality of blocks has a checksum field capable of containing a value. Any host system generates an error when data from a retrieved block from the plurality of blocks computes to a checksum that is different from the value contained within the checksum field for the retrieved block, and the retrieved block does not contain the initialization pattern.
    Type: Grant
    Filed: January 22, 2002
    Date of Patent: October 3, 2006
    Assignee: Sun Microsystems, Inc.
    Inventors: William L. Duncan, Wayne Ihde, Michael Tibbetts
  • Patent number: 7117216
    Abstract: Embodiments of the present invention relate to a method and apparatus for a runtime merging system of hierarchical trees with a reference node implementation. According to one or more embodiments of the present invention, a reference node is implemented which holds a reference to a node in a DOM tree active in memory. The reference node class allows adding nodes to the merged tree without having to make a clone of the node, which is an expensive operation. In one embodiment, if a particular node is not present below a certain level of the tree in any layer except a unique layer, it renders visiting the children of that node unnecessary. A reference is kept to the node in the memory.
    Type: Grant
    Filed: October 19, 2001
    Date of Patent: October 3, 2006
    Assignee: Sun Microsystems, Inc.
    Inventors: Krishnendu Chakraborty, Amy M. Wong, Joerg Heilig
  • Patent number: 7117382
    Abstract: Disclosed is a method and circuit for variably controlling a delay line for a read data capture timing window. In one embodiment, the circuit includes a variably controlled delay circuit coupled to a FIFO. The variably controlled delay circuit receives an input strobe signal. The variably controlled delay circuit also receives a multibit control code. The variably controlled delay circuit transmits the input strobe signal after a time delay, wherein the time delay varies according to the multibit control code. The FIFO is coupled to the variably controlled delay circuit and receives the time delayed strobe signal therefrom. The FIFO receives an input data bit signal. The FIFO stores the input data bit signal in response to receiving the time delayed strobe signal.
    Type: Grant
    Filed: May 30, 2002
    Date of Patent: October 3, 2006
    Assignee: Sun Microsystems, Inc.
    Inventors: Cong Q. Khieu, Louise Gu
  • Patent number: 7114994
    Abstract: A modular computer system includes at least one information processing module removably received at a first face of a housing, at least one computer support module removably received at a second face of the housing, at least one power supply module removably received at the second face of the housing, and a connections member. The connections member includes at least one connector at a first face of the member arranged to connect to a connector of the at least one information processing module. The connections member further includes at least one connector at a second face of the member arranged to connect to a connector of the at least one computer support module. The connections member also includes at least one connector at the second face of the member arranged to connect to a connector of the at least one power supply module.
    Type: Grant
    Filed: May 5, 2004
    Date of Patent: October 3, 2006
    Assignee: Sun Microsystems, Inc.
    Inventors: Paul J Garnett, Peter Heffernan
  • Patent number: 7117479
    Abstract: An editor or software engineering tool may be configured to render whitespace between adjacent tokens, wherein the amount of whitespace between any two adjacent tokens is determined according to language-specific style rules and scaled in accordance with display considerations. In some realizations, the operative scaling is selected or defined by a user according to the user's visual preferences. In some realizations, the operative scaling relates to requirements or constraints of an automated layout mechanism. For example, a particular scaling may be calculated to adjust line length in conformance with a desired margin alignment or to optimize layout when long lines are automatically wrapped (or folded) in some automatic way.
    Type: Grant
    Filed: October 1, 2001
    Date of Patent: October 3, 2006
    Assignee: Sun Microsystems, Inc.
    Inventor: Michael L. Van De Vanter
  • Publication number: 20060218557
    Abstract: In a multi-processor multi-threaded computer system, resources are dynamically assigned during program operation to either threads or processors in such a manner that resource usage is maximized. In one embodiment, the choice of whether to assign resources to threads or processors is dependent on the number of threads versus the number of processors. In another embodiment, when the system is operating in one assignment mode, the amount of wasted resources is measured and when this measured amount exceeds a predetermined threshold based on the maximum resources that could be wasted were the system operating in the other assignment mode, the assignment is switched to the other assignment mode.
    Type: Application
    Filed: March 25, 2005
    Publication date: September 28, 2006
    Applicant: Sun Microsystems, Inc.
    Inventors: Alexander Garthwaite, David Dice, Derek White