Abstract: One embodiment of the present invention provides a system for verifying type safety of an application snapshot. This application snapshot includes a state of an executing program that is moved from a first computing device to a second computing device across a network in order to continue execution on the second computing device. The system operates by receiving the application snapshot from the first computing device on the second computing device, wherein the application snapshot includes a subprogram, an operand stack, and a point of execution. The system then examines the application snapshot to identify one or more subprograms and the point of execution within the subprograms. Next, the system examines the subprogram to determine an expected structure of the operand stack at the point of execution.

Abstract: Disclosed are novel methods and apparatus for providing a permissions manager capable of assisting an applet, for example, in determination and/or grant of the permissions required for an operation. In an embodiment, an apparatus for managing permissions is disclosed. The apparatus includes a software application, a permissions manager coupled to the software application and receiving a request sent by the software application, and a programming environment coupled to the permissions manager. The request may indicate a permission, which may be requested by the permissions manager. The permissions manager may access the programming environment to determine a required permission corresponding to the permission and to determine how to grant the required permission.

Abstract: We present a methodology for transforming concurrent data structure implementations that depend on garbage collection to equivalent implementations that do not. Assuming the existence of garbage collection makes it easier to design implementations of concurrent data structures, particularly because it eliminates the well-known ABA problem. However, this assumption limits their applicability. Our results demonstrate that, for a significant class of data structures, designers can first tackle the easier problem of an implementation that does depend on garbage collection, and then apply our methodology to achieve a garbage-collection-independent implementation. Our methodology is based on the well-known reference counting technique, and employs the double compare-and-swap operation.

Abstract: A method and apparatus for controlling power consumption in a processor. In one embodiment, a processor includes a pipeline. The pipeline includes logic for fetching instructions, issuing instructions, and executing instructions. The processor also includes a power management unit. The power management unit is configured to input M stalls into the pipeline every N instruction cycles (where M and N are integer value and wherein M is less than N).

Abstract: An electronic system is described in which integrated circuits employing cornered I/O are arranged in a framework including an optional path manager and at least one updateable routing table. Packet routing options are described with solutions being provided to minimize transmission latency and pathway alternatives.

Abstract: A source multicasts information to a plurality of targets. The targets respond to the multicast information by sending acknowledgements that indicate receipt of the multicast information. The acknowledgements are merged into a merged acknowledgment, which is then supplied to the source. The source can determine from the merged acknowledgement whether the targets successfully received the multicast information.

Abstract: A method is provided for checking a computer system configuration in which a first check file is provided (28). A second check file is compiled (34) from the computer system configuration. The first and second check files are compared against each other (36) and a computer system configuration is approved (38) in dependence on the result of this comparison. This process can take place at the point of manufacture or at a customer installation or both.

Abstract: A system and method are disclosed for improving the remote display of graphics images by the redirection of rendering and the optional use of image data compression. Instead of sending graphics commands over a network and rendering on a remote computer system, graphics commands may be automatically redirected by modified OpenGL functions to local graphics devices without explicit involvement by the graphics application. The modifications to a set of the OpenGL functions on the local system are transparent in the normal mode of rendering and displaying locally. After an image is rendered locally, it may be read back and sent across the network. A standard X Server on the remote system may be sufficient to support this methodology. An X Extension for data decompression on the remote system, however, may allow for more efficient image transmission through the use of image data compression.

Abstract: An arbitration unit includes an input unit, a selection unit and an output unit. The input unit may receive a plurality of input requests on a plurality of inputs. The selection unit may prioritize inputs into a priority order and may also select up to two of the input requests having a higher priority than others of the plurality of input requests during a current arbitration cycle. The output unit may provide an output indicative of which of the plurality of input requests were selected. During a subsequent arbitration cycle, the selection unit may reprioritize the plurality of inputs depending upon which of the plurality of input requests were selected.

Abstract: A fault isolation system in a network is disclosed, particularly suited for use in a unidirectional fibre channel arbitrated loop. Information relating to read and write errors occurring on the loop is stored, and fault regions are located by determining areas on the loop downstream of write errors and upstream of read errors. The system may be extended to networks with bidirectional communications by storing directionality information with the detected errors. Command and response error information is not needed to deterministically locate the fault regions. When a given fault region is identified, loop and device diagnostics are executed for that region of the loop to specifically identify the failed components.

Abstract: There is described an arrangement for mounting removable components to electronics module of rack-mountable modular electronic circuits. The removable component is surrounded by a latching collar provided with resilient latching arms, the latching arms having detent surfaces which, when the removable component is fully inserted, engage interior surfaces of the module housing to prevent withdrawal. Gripping tabs attached to the latching arms extend outwardly through the insertion opening so as to be accessible when the module is mounted in a rack, the gripping tabs being operable to release the detents and permit withdrawal of the removal component without removing the module from the rack. The mounting arrangement is particularly applicable to DVD or other media drives, but can be used for other components such as power supplies.

Abstract: A floating point unit capable of converting a 64-bit integer number to a floating point format is provided. The floating point unit includes an 11-bit zero/one complement detect circuitry in an exponent datapath of the floating point unit, where the 11-bit zero/one complement detect circuitry is used to determine a shift count for a right shifter in a large exponent difference mantissa datapath of the floating point unit. The 11-bit zero/one complement detect circuitry determines shift counts based on particular bit groupings of the 64-bit operand.

Abstract: Methods, systems and programs for isolating faults in a network loop is described. The link between the last device and the initiator in the network loop is tested. The loop segment between the initiator and the last device in the network loop is testesd. If a faulty link is identified in the loop segment between the initiator and the last device, then a faulty loop segment is identified and the faulty link within the faulty loop segment is isolated. For various embodiment of the present invention, divide and conquer testing or other systematic testing methods may be used to isolate the faulty link.

Abstract: A graphics system comprising a series of calculation units. The calculation units comprise a first subset and a second subset of calculation units. A first calculation unit of the series generates a first digital video stream and a second digital video stream. Each calculation unit of the first subset: (a) passes the second digital video stream to a next calculation unit of the series unmodified; and (b) computes first pixel values, injects or mixes the first pixel values into the first digital video stream, and passes the modified first digital video stream to the next calculation unit. Similarly, each calculation unit of the second subset injects or mixes second pixel values into the second digital video stream, and passes the first digital video stream unmodified. A last calculation unit of the series drives one or more display devices in response to the first and second digital video streams.

Abstract: A sample-to-pixel calculation unit in a graphics system may comprise an adder tree. The adder tree includes a plurality of adder cells coupled in a tree configuration. Input values are presented to a first layer of adder cells. Each input value may have two associated control signals: a data valid signal and a winner-take-all signal. The final output of the adder tree equals (a) a sum of those input values whose data valid signals are asserted provided that none of the winner-take-all signals are asserted, or (b) a selected one of the input values if one of the winner-take-all bits is asserted. The selected input value is the one whose winner-take-all bit is set. The adder tree may be used to perform sums of weighted sample attributes and/or sums of coefficients values as part of pixel value computations.

Abstract: A flow manager may receive packet flow rules from one or more network services and may generate a unified rule set according to the received packet flow rules. A flow manager may additionally split the unified rule set into subsets for enforcement by one or more flow enforcement devices and may install the rule subsets onto the flow enforcement devices. When splitting the unified rule set into subsets, a flow manager may analyze a network topology connecting the flow enforcement devices. A flow manager may also receive additional packet flow rules, integrate them into the unified rule set, update the rule subsets according to the additional rules, and install the updated subsets onto the flow enforcement devices.

Abstract: One embodiment of the present invention provides an electronic circuit and method for measuring a capacitance. A signal generating mechanism generates a signal having a predefined frequency and predefined low and high voltage levels on one terminal of the capacitance. The other terminal of the capacitance is coupled to a switching mechanism. The switching mechanism is set to couple the other terminal of the capacitance to a first amplifier or a second amplifier for a portion of each signal cycle thereby full-wave rectifying a transient current flowing between the two terminals in the capacitance. Outputs of the first amplifier and the second amplifier are coupled to a current measurement mechanism for measuring the current. The capacitance is determined from the measured current. Several variations on this embodiment are provided.

Abstract: Techniques for generation of Java™ macro instructions suitable for use in Java™ computing environments are disclosed. As such, the techniques can be implemented in a Java™ virtual machine to efficiently execute Java™ instructions. As will be appreciated, a Java™ macro instruction can be substituted for two or more Java™ Bytecode instructions. This, in turn, reduces the number of Java™ instructions that are executed by the interpreter. As a result, the performance of virtual machines, especially those operating with limited resources, is improved. A Java™ macro instruction can be generated for conventional Java™ instruction sequences or sequences of Java™ instruction that are provided in a reduced set of instruction. In any case, sequences that are frequently encountered can be replaced by a Java™ macro instruction. These sequences are typically encountered when Java™ objects are instantiated, during programming loops, and when a local variables are assigned a value.

Abstract: Animated indicators monitor the state of a software container and reflect the state of the container, potentially including information such as amount, type, and activity of the container. As the state of the container changes, an animation routine accordingly changes. Users are presented with up-to-date and detailed information about a container represented by a small graphic pictorial. Thus, the user receives a continuous supply of useful information about the container without having to specifically select and view the container as a full screen representation.

Abstract: According to the invention, a processing core is disclosed. The processing core includes one or more processing pipelines and a number of register flies. The processing pipelines having a total of N-number of processing paths, where each of the processing paths processes instructions on M-bit data words. Each of the number of register files has Q-number of registers that are each M-bits wide. The Q-number of registers within each of the plurality of register files are either private or global registers. When a value is written to one of said Q-number of said registers, which is a global register within one of said number of register files, the value is propagated to a corresponding global register in the other of the number of register files. When a value is written to one of said Q-number of the registers, which is a private register within one of said number of register files, the value is not propagated to a corresponding register in the other of said number of register files.