Abstract: A data authentication system that at the sender produces for a plurality of data packets a plurality of “integrity checks” by selecting an integrity function from a family or set of integrity functions, selecting a number of bytes from a given packet and manipulating the bytes in accordance with the selected integrity function to produce the integrity check. The system then selects corresponding bytes or bytes that are offset from the corresponding bytes from a next packet and produces a next associated integrity check using the same or another selected integrity check function, and so forth. The system encrypts the integrity checks associated with the plurality of data packets using, for example, a shared secret key, and produces an integrity block. The system then sends the encrypted integrity block and the data packets to the intended recipients. A recipient decrypts the integrity block using the shared secret key and reproduces the integrity checks.

Abstract: Improved frameworks for loading and execution of portable, platform independent programming instructions within a virtual machine are described. The improved frameworks provides a mechanism that will generally improve the runtime performance of virtual machines by eliminating the need to always traverse a constant pool at runtime to execute a Java™ instruction. In addition, specific data structures that are suitable for use within a virtual machine and methods for creating such data structures are described. Accordingly, an enhanced Java™ bytecode representation having a pair of Java™ bytecode streams is disclosed. The enhanced Java™ bytecode has a Java™ code stream suitable for storing various Java™ commands as bytecodes within a code stream. A Java™ data stream of the enhanced Java™ bytecode representation is used to store the data parameters associated with the Java™ commands in the code stream. Actual parameter values, or references to actual parameter values can be provided in the data stream.

Abstract: A symmetric multiprocessor (SMP) system includes a plurality of central processing units (CPUs). Processing by a central processing unit (CPU) is safely halted i.e., a CPU is shut down, using a technique that assures that the CPU is executing an idle thread when the CPU is shut down. Halting the CPU safely means (a) that the CPU cannot be executing a thread other than the idle thread, and (b) that state information for a thread does not reside only within the CPU. The first limitation assures that the CPU cannot be executing a time critical thread that fails if the execution of the time critical thread has to move to another CPU.

Abstract: Methods, systems, and articles of manufacture consistent with the present invention limit access to parts of a shared software library by using a class loader that generates a selective interface between an external process and a program file (such as a class definition) in the shared library. This prevents external processes from loading parts of the shared library that were meant to remain private or internal to the library. Methods, systems, and articles of manufacture consistent with the present invention load a program file, such as a class definition, from the shared library and generate an interface (such as an object) to the loaded program file. A determination of whether the program file can be exported is performed based upon a status indicator associated with the interface. The interface limits access to the program file if it is determined that the program file cannot be exported.

Abstract: A memory controller includes a check/correct circuit and a data remap circuit. The check/correct circuit is coupled to receive an encoded data block from a memory comprising a plurality of memory devices. The encoded data block includes a plurality of check bits, and the check/correct circuit is configured to decode the encoded data block and to detect a failure of one of the plurality of memory devices responsive to decoding the encoded data block. The data remap control circuit is configured to cause a remap of each of a plurality of encoded data blocks to avoid storing bits in the failing memory device. A memory controller may also be configured to detect and correct a first failed memory device and a second failed memory device of the plurality of memory devices.

Abstract: A method for designing a software program including multiple modules includes defining an initialization sequence wherein each of the modules is initialized according to a predetermined order. The method also includes defining calling order constraints wherein a first module may call a second module if the first module succeeds the second module in the allowed order. The method also includes creating a program specification for the software program. The program specification includes a module specification for each of the modules and each module specification indicates other modules called by an implementation of the module. According to one aspect, one of a plurality of initialization sequences is selected based upon the presence of one or more markers in a memory.

Abstract: A system, including a first device comprising a first description and configured to provide a first service, wherein the first service provides a first interface accessible by a first port, and wherein the first description comprises a first device identifier, a first service identifier corresponding to the first service, a first interface identifier corresponding to the first interface, and a first port identifier corresponding to the first port, and an edge device configured to communicate with the first device and obtain the first description.

Abstract: One embodiment of the present invention provides a system that bounds the solution set of a system of nonlinear equations specified by the set of linear equations Ax=b, wherein A is an interval matrix and b is an interval vector. During operation, the system preconditions the set of linear equations Ax=b by multiplying through by a matrix B to produce a preconditioned set of linear equations M0x=r, wherein M0=BA and r=Bb. Next, the system widens the matrix M0 to produce a widened matrix, M, wherein the midpoints of the elements of M form the identity matrix. Finally, the system uses M and r to compute the hull h of the system Mx=r, which bounds the solution set of the system M0x=r.

Abstract: A system-on-a-chip device is provided, the system-on-a-chip device comprising an on-chip processor and an on-chip dynamic random access memory (DRAM) capable of communicating with the on-chip processor. The system-on-a-chip device also comprises at least one on-chip input/output (I/O) bus capable of communicating with the on-chip processor and the on-chip dynamic random access memory (DRAM).

Abstract: Modern programming languages have stimulated work on systems that dynamically compile or optimize frequently executed portions of programs. In practice, such systems typically rely on ad hoc heuristics. For example, a system may optimize (or compile) some code once its execution count exceeds a given threshold. An analytical model has been developed that expresses performance of such a system. In one embodiment, the model is based on a bytecode frequency histogram, which indicates (for a given program) how many bytecodes run for how many times. It predicts that the optimal compilation threshold will occur where the hazard rate falls through the reciprocal of the break-even point, the number of times a compiled bytecode must be executed to recoup its compilation time. Based on the insight provided by the model, a dynamic compilation control technique has been developed.

Abstract: A method and apparatus for fast initialization of storage devices. An apparatus is described including a redundant array of storage devices that comprises a logical volume of storage. The logical volume further comprises a plurality of stripes. A bit mapped vector provides state initialization information for each of the plurality of stripes in lieu of initializing each of the stripes. A storage controller initializes each of the plurality of stripes by using accesses to the redundant array while concurrently allowing access to the plurality of stripes. Initialization of a stripe can be done by processing a write access. Associated written data to the stripe and updating its corresponding redundancy effectively initializes that stripe. The bit mapped vector is updated to reflect the initialization of that stripe. In addition, while the redundant array is idle, further initialization of un-initialized stripes occurs while concurrently allowing access to the redundant array.

Abstract: An extended exponent floating point unit performs an extended exponent floating point operation on a plurality of operands to produce a product of the plurality of operands. The extended exponent floating point unit groups the plurality of operands into at least one group, determines a plurality of scale factors for the plurality of operands, respectively, and provides a running sum of the plurality of scale factors. The extended exponent floating point unit further scales the plurality of operands to obtain a plurality of scaled operands, multiplies the plurality of scaled operands to obtain a group product, and scales the group product to obtain a scaled group product. The scaled group product is adjusted based on the running sum. The plurality of operands are grouped such that when all the plurality of scaled operands in the at least one group are multiplied an overflow or underflow will not occur.

Abstract: A method for synchronizing a data signal and a clock signal has been developed. The method first generates two separate intermediate data signals. The intermediate data signals lag the input data signal. The separate durations of the two lagging signals are combined to form an output data signal that is synchronized with the system clock signal.

Abstract: A containment framework sufficiently compact and efficient to run on a wide variety of resource-constrained, small footprint devices, such as personal data assistants (PDAs), smart cellular phones, global positioning system (GPS) receivers, etc. The containment framework may support services which integrate with network-based services to deliver personalized content to small footprint device users.

Abstract: A system and method for calculating a deadlock-free free set of paths in a network generates an ordered set of deadlock-free sub-topologies, referred to as “layers.” The ordered set of layers is then used to determine a deadlock-free set of paths through the network by performing a shortest-path route calculation with the following constraint: starting at any given layer, for each node, proceed to calculate a shortest path to every other node in the graph where, at any node being utilized to assess a given minimum path, the path may move to any higher-ordered layer, but may not return to a lower-ordered layer.

Abstract: A system for cooling electronic assemblies includes an equipment enclosure configured to receive a plurality of electronic assemblies in a plurality of mounting locations. The system also includes a cooling manifold that is mounted to the equipment enclosure and positioned to distribute chilled air to each of the electronic assemblies through a plurality of orifices.

Abstract: The present invention relates to a management agent that can be ran on any operating system. More specifically, the management agent of the present invention is implemented with a set of application program interfaces (APIs) that allows the management agent to be independent of operating systems. The APIs makes the management agent portable across multiple operating systems. In an embodiment of the present invention, a Compact Peripheral Component Interconnect (CPCI) computer system includes a CPCI chassis, a circuit board located within the CPCI chassis, a first central processing unit (CPU) card coupled with the circuit board. The CPCI computer system also includes a second CPU card coupled with the circuit board, a first management agent located within the first CPU card, and a second management agent located within the second CPU card. The first and second CPU cards each respectively has a first operating system and a second operating system.

Abstract: Various embodiments of a method and system for inhibiting reads to non-guaranteed data in remapped portions of a storage medium are disclosed. In one embodiment, a method of managing a non-read list associated with a storage medium involves: detecting a bad portion of the storage medium, remapping the bad portion's address to a new portion of the storage medium, copying the data stored to the bad portion to the new portion and, if the copy is unsuccessful, adding the address of the new portion to the non-read list, and inhibiting a read to the new portion if the new portion's address is listed on the non-read list. The address of the new portion may be removed from the non-read list in response to a successful write to the new portion.

Abstract: One embodiment of the present invention provides a system for verifying type safety of an application snapshot. This application snapshot includes a state of an executing program that is moved from a first computing device to a second computing device across a network in order to continue execution on the second computing device. The system operates by receiving the application snapshot from the first computing device on the second computing device, wherein the application snapshot includes a subprogram, an operand stack, and a point of execution. The system then examines the application snapshot to identify one or more subprograms and the point of execution within the subprograms. Next, the system examines the subprogram to determine an expected structure of the operand stack at the point of execution.

Abstract: We present a methodology for transforming concurrent data structure implementations that depend on garbage collection to equivalent implementations that do not. Assuming the existence of garbage collection makes it easier to design implementations of concurrent data structures, particularly because it eliminates the well-known ABA problem. However, this assumption limits their applicability. Our results demonstrate that, for a significant class of data structures, designers can first tackle the easier problem of an implementation that does depend on garbage collection, and then apply our methodology to achieve a garbage-collection-independent implementation. Our methodology is based on the well-known reference counting technique, and employs the double compare-and-swap operation.