Abstract: The present invention provides an efficient implementation of multiprecision arithmetic, such as for a microprocessor. For example, an implementation of multiprecision arithmetic is provided that eliminates condition codes, such as condition codes for a carry bit and a borrow bit, and eliminates an add-with-carry instruction for multiprecision addition and a subtract-with-borrow instruction for multiprecision subtraction. In one embodiment, a method includes separately performing a first one or more arithmetic operations and a second one or more arithmetic operations. The second arithmetic operations indicate if the first arithmetic operations cause a carry condition or if the first arithmetic operations cause a borrow condition. The one or more results of the first and second arithmetic operations are then provided. The first and second arithmetic operations can be executed in parallel on a microprocessor.

Abstract: A system is presented for latching and amplifying a capacitively coupled inter-chip communication signal that operates by receiving an input signal on a capacitive receiver pad and feeding the input signal through an inverter to produce an output signal. The output signal is fed back through a weakened inverter to produce a feedback signal that is fed into an input of the inverter to form a latch for the input signal. The weakened inverter is biased to produce a feedback signal that swings between a high bias voltage, VH, and a low bias voltage, VL. VH is set slightly higher than the switching threshold of the inverter, and VL is set slightly lower than the switching threshold. This feedback signal causes the input signal to reside within a narrow voltage range near the switching threshold of the inverter, thereby making the inverter sensitive to small transitions in the input signal.

Abstract: A mechanism for servicing connections by disassociating processing resources from idle connections and monitoring the idle connections for activity is described. In one embodiment, a connection that is being serviced by a processing resource is disassociated from the processing resource when the connection is idle. The connection is handed to a poll manager for placement into one of several poll subsets. A poll thread associated with each poll subset is sends the poll subsets and poll requests to a poll adapter. The poll adapter uses the features of the operating system to monitor the connection for activity, such as by polling the connections to identify any pending events. The approach may be implemented on different operating systems by changing the poll adapter. The poll manager passes active connections to a work queue to wait for servicing. The present invention avoids wasting resources on connections that are idle.

Abstract: A system and method for processing a variable looping statement into a constant looping statement to enable loop unrolling. A lower bound and an upper bound of the loop index within the variable looping statement are determined. A constant looping statement is then formed using the lower bound and upper bound to define a range over which the loop index varies within the constant looping statement. The constant looping statement further includes a conditional statement that reflects conditions in the initial expression and/or the exit expression of the variable looping statement. The conditional statement controls execution of the body of the generated constant looping statement, which includes the body from the original variable looping statement. Loop unrolling may then be performed on the generated constant looping statement.

Abstract: A system and method for dynamically tuning the interrupt coalescing behavior of a communication interface. An interrupt handler adjusts dynamic Packet and/or Latency values to control how many packets the interface may accumulate, or how much time the interface may wait after receiving a first packet, before it can signal a corresponding interrupt to a host processor and forward the accumulated packet(s). The interrupt handler maintains a Trend parameter reflecting a comparison between recent sets of packets received from the interface and the Packet parameter. The Packet value is decreased or increased as packet traffic ebbs or flows. When the Packet value is incremented from a minimum value, a Fallback mechanism may be activated to ensure a relatively rapid return to the minimum value if an insufficient amount of traffic is received to warrant a non-minimum Packet value. The Latency value may be increased as the processor's workload increases.

Abstract: The present invention provides a method and apparatus for statement boundary detection. In one embodiment of the present invention, a parser determines a natural end of a statement, where possible, based upon the context of the input stream and the syntax of the programming language. Thus, no statement terminator is necessary when a natural end to a statement is determined. The parser uses the natural end of a statement to terminate one statement and begin parsing another statement. In one embodiment, a special statement termination token is required to terminate a statement when no natural statement end exists. In another embodiment, a special statement termination token can be used to terminate a statement when a natural end of the statement exists.

Abstract: A method for dynamic implementation of a Java™ Metadata Interface (JMI) to a metamodel includes receiving a JMI implementation request, implementing a package proxy JMI interface when the request is a package proxy request, implementing a class proxy JMI interface when the request is a class proxy request and implementing a class instance JMI interface when the request is a class instance request. The request is associated with a metamodel that includes at least one package. The at least one package includes at least one class. The at least one class includes at least one attribute reference or operation.

Abstract: A control unit for a graphics accelerator. The control unit includes a plurality of processing pipelines, a memory (configured to store an allocation table) and a context management unit. The context management unit is configured to: (a) receive a graphics command, (b) decode a process identifier from input data provided in or with the graphics command, wherein the process identifier corresponds to one of a plurality of host processes executing on one or more central processing units external to the graphics accelerator, and (c) identify an entry E in the allocation table that corresponds to the process identifier. In response to a first set of conditions, the context management unit is further configured to: (d) reassign ownership of a first of the processing pipelines from a first active entry of the allocation table to the entry E, and (e) send the graphics command to the first processing pipeline.

Abstract: One embodiment of the present invention provides a system that detects violations of type rules in a computer program. The system operates by locating a type casting operation within the computer program, wherein the type casting operation involves a first pointer and a second pointer. The system then checks the type casting operation for a violation of a type rule. If a violation is detected, the system indicates the violation. In one embodiment of the present invention, if the first pointer is defined to be a structure pointer and the second pointer is not defined to be a structure pointer, the system indicates a violation of a type rule. In one embodiment of the present invention, if the first pointer is defined to point to a first structure type and the second pointer is defined to point to a second structure type, the system determines whether the first structure type and the second structure type belong to the same alias group. If not, the system generates an error to indicate a type violation.

Abstract: Through the association of an IP address with each data stream, a single system may be used by a network card or a tuner to select multicast IP data. Each data stream is identified by a unique IP address. More particularly, a locator adapted for identifying a data stream is associated with one of a plurality of data streams. The locator is then mapped to an IP address. When it is determined that the IP address corresponds to a data stream locator associated with a data stream, a tuner is instructed to read the data stream associated with the data stream locator. However, when it is determined that the IP address does not correspond to a data stream locator, a network card identified by the IP address is instructed to read data from the associated network. Since each data stream may be associated with a plurality of multicast IP addresses, a multicast group address is specified to identify the appropriate multicast IP data transmitted in the data stream.

Abstract: A Java preprocessor method is provided. A Java template file is received that includes Java programming language code and meta code. The Java template is then processed to create an intermediate program using the meta code, wherein the intermediate program is a Java program. The intermediate program is compiled to create an intermediate class, which is a Java based class, and an object text file is generated using the intermediate class.

Abstract: Access is provided in an object-oriented computing environment by an instance of a first class to a selected protected resource of an instance of a second class. This involves defining a third class that includes a protected virtual method for accessing the selected protected resource. The first class is defined as a subclass of the third class such that the first class inherits from the third class an access-resource method for the protected resource and a pointer to an instance of the second class as an implementation of the third class. The second class is defined as a subclass of the third class such that the second class inherits from the third class and implements the protected virtual method for accessing the selected protected resource by overloading that method.

Abstract: A method for analyzing input output (I/O) pin arrangements to determine the effect of differential pair and power and ground pin placement on signal quality which includes constructing an array of pins, arranging a plurality of differential pairs within the array of pins to provide a pin arrangement, exciting each of the differential pairs within the pin arrangement, monitoring coupled noise on other differential pairs within the pin arrangement, and analyzing the pin arrangement based upon the monitoring.

Abstract: A lightweight global distribution mechanism distributes packages within a distributed system. The packages may hold any type of content and may hold contents such as patches, programs, documents or files. The distribution mechanism is lightweight in that it incurs minimal computational and memory overhead. With the distribution mechanism, a package index that identifies packages for installation is stored at a publishing master. Client systems may access and analyze the package index to determine which packages to install. The client systems may hold subscription lists that identify the packages to which the clients subscribe. The packages need not be stored at the publishing master but rather may be stored at separate repositories.

Abstract: A method for automatically generating front-end code and back-end code that are both compatible with a specification, such as the JDWP communication protocol. First, a detailed protocol specification is written that contains a description of a communication protocol between the front-end code and the back-end code. The detailed specification is then input into a code generator that parses the specification. The front-end code is then automatically generated from the formal specification, and may be written in a first computer language such as the Java™ programming language. The code generator then generates the back-end code, which may be written in a second computer language such as C.

Abstract: Methods and systems consistent with certain aspects related to the present invention provide a digital network having a plurality of data storage elements, at least one client, and a switch element. The switch element may be operable to receive access requests from the client and provide access to data on the storage elements in response to one or more access requests.

Abstract: A graphics system comprising a scheduling network, a sample buffer and a plurality of filtering units. The sample buffer is configured to store sample generated by a rendering engine. The plurality of filtering units are coupled in a linear series. Each filtering unit of the linear series is configured to send a request for a scanline of sample bins to a first filtering unit of the linear series. The first filtering unit is configured to service the scanline requests by sending burst requests to a scheduling network and coordinating the flow of samples forming the bursts from the sample buffer to the filtering units.

Abstract: A method and system makes inlining decisions that are efficient for subprograms that have significantly varying execution times over a range of variables or execution paths. A subprogram of a computer program is identified and certain execution paths of the subprogram are selectively inlined. The subprogram may be identified based on execution characteristics of the subprogram. The selective inlining of the execution paths may be based on execution characteristics of the paths. The paths may be selectively inlined based on an inline indication associated with an execution path, where the inline indication may be an inline directive. The inline directive may be included as part of a program comment statement. A compiler makes determinations whether to inline a specific execution path of a subprogram by evaluating certain information supplied in conjunction with the path.

Abstract: A multiprocessing system including multiple processing nodes employs various implementations of hierarchical back-off locks. A thread attempting to obtain a software lock may determine whether the lock is currently owned by a different node than the node in which the thread is executing. If the lock is not owned by a different node, the thread executes code to perform a fast spin operation. On the other hand, if the lock is owned by a different node, the thread executes code to perform a slow spin operation. In this manner, node locality may result wherein a thread that is executing within the same node in which a lock has already been obtained will be more likely to subsequently acquire the lock when it is freed in relation to other contending threads executing in other nodes.

Abstract: A multiple-core processor with support for multiple virtual processors. In one embodiment, a processor may include a cache including a number of cache banks, a number of processor cores and core/bank mapping logic coupled to the cache banks and processor cores. During a first mode of processor operation, each of the processor cores may be configurable to access any of the cache banks, and during a second mode of processor operation, the core/bank mapping logic may be configured to implement a plurality of virtual processors within the processor. A first virtual processor may include a first subset of the processor cores and a first subset of the banks, and a second virtual processor may include a second subset of the processor cores and a second subset of the cache banks. Subsets of processor cores and cache banks included in the first and second virtual processors may be distinct.