Abstract: A keyboard contains an input device comprising a linear strip of sensitive material the approximate width of the human finger integrated into the left or right side of the keyboard. The strip is linearly sensitive in only one direction and not to any other direction, such as from left to right. A user operates the device by touching it with his or her finger and varies the input by changing the position along the strip and the pressure of his or her finger.

Abstract: A linked-list-based concurrent shared object implementation has been developed that provides non-blocking and linearizable access to the concurrent shared object. In an application of the underlying techniques to a deque, the linked-list-based algorithm allows non-blocking completion of access operations without restricting concurrency in accessing the deque's two ends. The new implementation is based at least in part on a new technique for splitting a pop operation into two steps, marking that a node is about to be deleted, and then deleting it. Once marked, the node logically deleted, and the actual deletion from the list can be deferred. In one realization, actual deletion is performed as part of a next push or pop operation performed at the corresponding end of the deque.

Abstract: A method and apparatus for post-fabrication calibration and adjustment of a phase locked loop leakage current is provided. The calibration and adjustment system includes an adjustment circuit that adjusts a leakage current offset circuit to compensate for the leakage current of a capacitor. The capacitor connects to a control voltage of the phase locked loop. Such control of the leakage current in the phase locked loop allows a designer to achieve a desired phase locked loop operating characteristic after the phase locked loop has been fabricated. A representative value of the amount of compensation desired in the leakage current may be stored and subsequently read to adjust the phase locked loop.

Abstract: A system and method is provided for scan control and observation of a logical circuit that does not halt the operation of the system clock. Thus, all dynamic circuits within the system continue to evaluate and precharge normally. Moreover, the traditional method of placing a multiplexer before the data input of a clocked storage element to perform scan control and observation is no longer required. Consequently, the system and method provide a more efficient manner in which to perform scan control and observation of a logical circuit.

Abstract: Methods and systems for evaluating policies for load balancing in a network environment are disclosed. A switch provides load balancing of requests among different servers using an expression tree comprising data structures of precompiled executable code to determine an appropriate server group for sending traffic. When the switch receives a network request, such as an HTTP request, a policy evaluation processor executes the precompiled executable code to identify a group of network servers for servicing the request and forwards the request to the selected group of network servers. The request can be load balanced among the selected server group through any suitable load-balancing algorithm.

Abstract: One embodiment of the present invention provides a system that uses electrostatic forces to align semiconductor chips relative to each other. The system operates by fabricating a first set of conductors on the top surface of a first chip and fabricating a corresponding second set of conductors on the top surface of a second chip. To align the chips, the system electrically charges the first set of conductors and the second set of conductors. The system also places the first chip face-to-face with the second chip, so that the first set of conductors is in close proximity to the second set of conductors. This allows electrostatic forces between the first set of conductors and the second set of conductors to bring the first chip into alignment with the second chip and to hold them in place.

Abstract: A system and method are provided for sensing a physical stimulus of an integrated circuit. The system and method operate with one or more active thermal sensors embedded in the die of an integrated circuit to provide highly accurate die temperature measurements. The system and method are able to monitor and control the die temperature of the integrated circuit to avoid an integrated circuit malfunction due to an undesirable temperature condition.

Abstract: Method and apparatus for transmitting messages between communication devices via a communication channel allowing at least voice messages to be transmitted, the messages including data subdivided in a sequence of basic data units, the method including; a) encoding the basic data units as unique signals (usj) including a predetermined number of basic signals (bi), each basic signal having a unique fixed frequency (fi); b) transmitting a sequence of unique signals (usj) during a sequence of fixed time periods (t1, t2, t3, . . .); c) receiving and decoding the sequence of unique signals (usj) into the sequence of basic data units; the data being transmitted in superposition over voice.

Abstract: A method and apparatus for performing a built-in self-test (“BIST”) on an integrated circuit device are disclosed. A BIST controller comprises a BIST engine and a register. The BIST engine is capable of executing a built-in self-test and storing the results thereof, wherein the results include an indication of whether an executed built-in self-test is completed. The register is capable of storing the results of the executed built-in self-test, including the indication. A method for performing a built-in self-test comprises performing a BIST, including generating a indication of whether the built-in self-test is completed, and storing the indication.

Abstract: An efficient method of sub-typing an object in an object oriented computing environment is provided. In one embodiment, the sub-typing method loads an input object having an object type, whereby an embedded array and a cache are searched for an object sub-typing data structure corresponding to the requested supertype. Any found object sub-typing data structures are associated with the input object. In some embodiments, if the object sub-typing data structure is not initially found, an overflow array is searched and the cache is updated with the object sub-typing data structure when the object sub-typing data structure is included in the overflow array. A system and software product is further provided in other embodiments whereby information associated with a particular object sub-type is obtained.

Abstract: The precharge circuit includes circuitry for initiating charging of a precharge pulse at a first edge of a first clock-like signal. The precharge circuit also includes circuitry for ending the charging of the precharge pulse after a time period that is longer of a preset delay period and a time period designated by a second edge of the second clock-like signal.

Abstract: A method for deriving an application specification from an enterprise application including mapping the enterprise application to obtain a plurality of states and a plurality of transitions, monitoring the enterprise application to obtain a list of variable usages for each of the plurality of states, parsing source code of the enterprise application to obtain process logic for each of the plurality of transitions, and deriving the application specification using each of the plurality of states, the plurality of transitions, the list of variable usages for each of the plurality of states, and the process logic for each of a plurality of transitions.

Abstract: One embodiment of the present invention provides a system that dynamically compiles byte codes into native code to facilitate faster execution. This method operates in a mixed-mode system that supports execution of both compiled code and interpreter code. During operation, the system periodically determines if a currently executing thread is executing through the interpreter. If so, the system locates the method being executed by the thread and compiles the byte codes of the method into native code. Subsequent executions of the method utilize the faster-executing native code.

Abstract: An apparatus for performing a block operation includes a functional unit, which performs an operation on one or more block operands, and an accumulator memory. The accumulator memory includes two independently interfaced memory banks. A control unit controls the memory banks in the accumulator memory so that each time the operation is performed, an operand is provided from one of the memory banks and a result is stored in the other memory bank. Since the memory banks are independently interfaced, the operand may be provided at the same time as the result is being stored. Additionally, since the result is stored in a different memory bank than the operand, the operation may be restarted if an error occurs.

Abstract: Data volumes on local hosts are discovered and managed by federated Java beans that run on each host. The Java beans form part of a three-tiered data services management. The lowest tier comprises management facade software running on each machine that converts platform-dependent interface written with the low-level kernel routines to platform-independent method calls. The middle tier is a set of federated Java beans that communicate with the management facades and with the upper tier of the system. The upper tier of the inventive system comprises presentation programs that can be directly manipulated by management personnel to view and control the system. The federated beans can configure and control data volumes with either a SCSI terminal emulation interface or a storage volume interface and use a logical disk aggregator to present all volumes available on a local host as a single “logical volume” in which all information regarding the various volumes is presented in a uniform manner.

Abstract: A memory subsystem including memory modules having multiple banks. A memory subsystem includes a memory controller and a plurality of memory modules. The plurality of memory modules may be coupled to the memory controller by a memory interconnect having a data path including a plurality of data bits. Each of the plurality of memory modules includes a circuit board and a plurality of memory chips mounted to the circuit board. The circuit board includes a connector edge for connection to the memory interconnect. Each of the plurality of memory chips may be configured to store data in a plurality of storage locations. Each of the plurality of memory modules may be coupled to a respective mutually exclusive subset of the plurality of data bits.

Abstract: A certificate validation mechanism is provided for a network interface. The certificate validation mechanism maintains a certificate cache containing local copies of certificates with associated validity indications. The certificate validation mechanism is operable to compare a certificate associated with a received message to the certificate cache and, where the certificate associated with the received message is held in the certificate cache, to associate with the message an indication of validity retrieved from the certificate cache. By providing a cache for certificates local to the network interface, the need always to verify a certificate by reference to a public repository is removed. If a certificate is not held in the local cache, then it can still be necessary to query the public repository. Nevertheless, the verification mechanism provides more immediate verification of certificate validity as this can be made locally without the cost and time of the remote verification at the public repository.

Abstract: Improved techniques for representation of Java string objects are disclosed. The techniques can be implemented to create Java string objects as arrays of one-byte characters when it is appropriate. To create Java string objects, an enhanced constructor can be provided in a Java library that is available to application programs (or programmers). In addition, enhanced Java methods can also be provided in the Java library. An array representation flag can optionally be allocated in the Java string object representation. The array representation flag can indicate whether the Java string object is allocated as an array of one-byte or an array of two-byte characters. Alternatively, the element type of the array can be referenced by using one or more references to determine whether the Java string object has been allocated as an array of one-byte or as an array of two-byte characters.

Abstract: A data authentication system that at the sender produces for a plurality of data packets a plurality of “integrity checks” by selecting an integrity function from a family or set of integrity functions, selecting a number of bytes from a given packet and manipulating the bytes in accordance with the selected integrity function to produce the integrity check. The system then selects corresponding bytes or bytes that are offset from the corresponding bytes from a next packet and produces a next associated integrity check using the same or another selected integrity check function, and so forth. The system encrypts the integrity checks associated with the plurality of data packets using, for example, a shared secret key, and produces an integrity block. The system then sends the encrypted integrity block and the data packets to the intended recipients. A recipient decrypts the integrity block using the shared secret key and reproduces the integrity checks.

Abstract: A symmetric multiprocessor (SMP) system includes a plurality of central processing units (CPUs). Processing by a central processing unit (CPU) is safely halted i.e., a CPU is shut down, using a technique that assures that the CPU is executing an idle thread when the CPU is shut down. Halting the CPU safely means (a) that the CPU cannot be executing a thread other than the idle thread, and (b) that state information for a thread does not reside only within the CPU. The first limitation assures that the CPU cannot be executing a time critical thread that fails if the execution of the time critical thread has to move to another CPU.