Abstract: A circuit board assembly that includes a circuit board. The circuit board includes a plurality of electrical contacts. The circuit board assembly also includes a solder cover that covers the electrical contacts. The solder cover includes a cover and a sliding-flange that is coupled to the cover. The circuit board assembly includes a retainer for restraining the solder cover. The retainer includes a mounting-flange and a retaining-flange.

Abstract: A memory expansion module with stacked memory packages. A memory module is implemented using stacked memory packages. Each of the stacked memory packages contains multiple memory chips, typically DRAMs (dynamic random access memory). The memory may be organized into multiple banks, wherein a given memory chip within a stacked memory package is part of one bank, while another memory chip in the same package is part of another bank. The memory module also includes a clock driver chip and a storage unit. The storage unit is configured to store module identification information, such as a serial number. The storage unit is also configured to store information correlating electrical contact pads on the module with individual signal pins on the stacked memory packages. This may allow an error to be quickly traced to a specific pin on a stacked memory package when an error is detected on the memory bus by an error correction subsystem.

Abstract: A system, method and apparatus for comparing two floating point numbers is includes choosing a first floating point number and a second floating point number to be compared. The first number is sign extended one bit to create a first sign extended number. The second number is sign extended one bit to create a second sign extended number. The second sign extended number is subtracted from the first sign extended number to determine a subtraction result. The sign bits for said first number and said second number are examined to determine if they are both ones. If the sign bits for the first number and the second number are both ones, the sign bit of the subtraction result is inverted to create a final result. If the sign bit of the final result is a zero, asserting that the first number is greater than or equal to the second number. Alternatively, if the sign bit of the final result is a one, asserting that the first number is less than the second number.

Abstract: One embodiment of the present invention provides a multiprocessor system that includes a number of processors with higher-level caches that perform memory accesses through a lower-level cache. This multiprocessor system also includes a reverse directory coupled to the lower-level cache, which includes entries corresponding to lines in the higher-level caches, wherein each entry identifies an associated entry in the lower-level cache. In one embodiment of the present invention, the higher-level cache is a set-associative cache, and storing the information within the reverse directory specifies a way location in the higher-level cache in which the line is to be stored. The system is configured to use this way information during a subsequent invalidation operation to invalidate the line in the higher-level cache without having to perform a lookup in the higher-level cache to determine the way location of the line in the higher-level cache.

Abstract: A multi-level cache and method for operation of a multi-level cache generating multiple cache system accesses simultaneously. Each access request includes an address identifying a memory location having data that is a target of the access. A insertion pointer inserts each access request into an entry in a memory scheduling window. Each entry is marked as valid when that entry is ready to be applied to a first cache level. A picker picks valid entries from the memory scheduling window by pointing to the picked entry and applying the address therein to the first cache level. The picking occurs in a free-running mode regardless of whether the accesses hit in the first cache level. A second cache level, receives accesses that have missed in the first cache level. A resource monitor in the second cache level determines when a predetermined number of resources are committed to servicing the accesses that have missed in the first cache level.

Abstract: A testbench for an integrated circuit (IC) design including a chain of scan circuits having a memory characteristic is verified by: (a) dividing the chain of scan circuits and creating a plurality of partitions, each partition including at least one logic cone output, each scan circuit belonging to one of the partition as a logic cone output; (b) generating a partitioned netlist for each partition from a full netlist for the IC design, the partitioned netlist including at least one logic cone, the logic cone extending from the logic cone output to at least one logic cone input; (c) generating a partitioned testbench for each partition from the full testbench based on the partitioned netlists; and (d) performing verification for the testbench by simulating the partitioned testbenches on the corresponding partitioned netlists.

Abstract: Improved techniques for accessing Java class files are disclosed. The techniques provide a mechanism that will generally improve the efficiency of virtual machines by providing a directory for Java class files. The directory can be implemented as an attribute in the attribute portion of the Java class files. Various components of the Java class file can be accessed efficiently by using the directory. In addition, techniques for accessing various components of Java class files using directories are disclosed. The techniques utilize the directory to allow efficient access to the class file. Thus, unlike conventional techniques, there is no need to perform sequential reads in order to locate various components of the Java class file. This allows for better use of resources. As a result, the invention can improve the performance of virtual machines, especially those that operate with limited resources (e.g., embedded systems).

Abstract: An apparatus and method for distributing multiple clock signals to multiple devices using an encoded clock signal is provided. A source clock signal can be encoded to result in an encoded system clock. The encoded system clock can be distributed to multiple devices in a computer system. The devices can decode the encoded system clock signal to generate a system clock signal and a global clock signal. The system clock signal and the global clock signal can then be distributed to their respective clock loads on each device. In certain embodiments, additional information, such as state information, can be encoded into the encoded system clock. A device can be configured to decode the additional information and can alter its state accordingly.

Abstract: The present invention pertains to techniques for creating and maintaining objects in object-oriented environments. The techniques are especially well suited for Java programming environments. In accordance with one aspect of the invention, specialized Java heaps are disclosed. In contrast to conventional heaps, the specialized Java heap is designated for storing Java objects with similar traits in the same memory portion. As such, objects with similar traits can be allocated and maintained in a designated memory portion. Another aspect of the invention provides methods for allocating objects in the heap memory. These methods can be used to create and associate objects with similar traits in a specialized heap. As will be appreciated, objects can be created and maintained more efficiently in this manner. As a result, the performance of virtual machines, especially those operating with relatively limited resources (e.g., embedded systems), is improved.

Abstract: A method allocates computing resources from a resource pool. Each job request includes attributes and a unique identifier. A digital signature is generated for each job request based on the combination of the attributes. The identifier is associated with the digital signature. Job requests having identical attributes are grouped together.

Abstract: We propose a new form of software transactional memory (STM) designed to support dynamic-sized data structures, and we describe a novel non-blocking implementation. The non-blocking property we consider is obstruction-freedom. Obstruction-freedom is weaker than lock-freedom; as a result, it admits substantially simpler and more efficient implementations. An interesting feature of our obstruction-free STM implementation is its ability to use of modular contention managers to ensure progress in practice.

Abstract: An existing neutral operating system (OS) signal is utilized to notify a virtual machine (VM) about a change to its execution parameters. The signal is predefined to indicate that an execution parameter should be changed, and upon receipt, the VM may look up a file in a predefined location, the file containing the new command line parameters. The VM may then modify its parameters to match the file, and continue with its execution, thus providing a mechanism for altering VM execution parameters at runtime.

Abstract: Speculative prefetching during DMA reads in a message-passing, queue-oriented bus system is controlled by creating a special data structure, called a “DMA scoreboard”, for each work queue entry associated with a DMA read. The DMA scoreboard tracks the completion of DMA writes and reads by monitoring acknowledgements received from DMA writes and data tags received from DMA read responses. The DMA scoreboard also contains a section that indicates the current PCI address, and size and number of prefetches to be performed. After a DMA read has completed, the PCI current address is incremented to obtain a new PCI address for the first prefetch request. A new work queue entry is then created from the information in the DMA scoreboard to perform the prefetch.

Abstract: Embodiments of the present claimed invention utilize video imaging to analyze the availability of parking spaces. In one embodiment, a computer is used to process video images of a parking location to determine if a parking space is available. In another embodiment of the present claimed invention, the type of parking space is also considered. For example, the system can distinguish between a compact parking space and a full-size parking space and direct vehicles to the appropriate parking space. This distinction becomes important when the optimization of space for parking in a crowded area is desired. Additionally, wireless communication can be used to deliver information regarding vacant parking spaces to motorists. Furthermore, embodiments of the present invention incorporate a global positioning system (GPS) to provide location dependent parking availability to motorists. For example, a motorist can request the location of the closest available parking space by pressing a button inside the vehicle.

Abstract: Provided is a method, system, program, and data structure for applying a patch to a computer system, wherein the patch includes content to add to the computer. A computer object is generated to include configuration information on the determined installed components. At least one patch includes content to add the computer and is capable of being associated with at least one realization, wherein each realization defines a state of the computer. For each realization, a determination is made from the configuration information in the computer object as to whether the state defined by the realization exists in the computer. Data is written to the computer object indicating whether the state defined by the realization exists on the computer. The computer object is used to determine whether each patch is compatible with the installed components of the computer.

Abstract: An enhanced Java Bytecode verifier suitable for operation in a Java computing environment is disclosed. The enhanced Java Bytecode verifier operates to determine whether one or more Java conventional Bytecode commands within a stream of Bytecodes are likely to place a reference to a Java object on the execution stack. In one embodiment, the conventional Java Bytecode commands identified as such are translated by the enhanced Java Bytecode verifier into one or more corresponding Java commands. When a corresponding command is executed, the reference associated with the conventional Java command is placed on a reference stack as well as the execution stack.

Abstract: We introduce obstruction-freedom—a new non-blocking condition for shared data structures that weakens the progress requirements of traditional nonblocking conditions, and as a result admits solutions that are significantly simpler and more efficient in the typical case of low contention. We demonstrate the merits of obstruction-freedom by showing how to implement an obstruction-free double-ended queue that has better properties than any previous nonblocking deque implementation of which we are aware. The beauty of obstruction-freedom is that we can modify and experiment with the contention management mechanisms without needing to modify (and therefore reverify) the underlying non-blocking algorithm. In contrast, work on different mechanisms for guaranteeing progress in the context of lock-free and wait-free algorithms has been hampered by the fact that modifications to the “helping” mechanisms has generally required the proofs for the entire algorithm to be done again.

Abstract: An interface for a distributed processing framework (DPF) is disclosed. The distributed processing framework (DPF) can manage the execution of a process utilizing cross-platform dynamically networked distributed computer system. The interface to the distributed processing framework (DPF) can be implemented as a graphical user interface. The graphical user interface allows users to conveniently communicate with the distributed processing framework. The graphical user interface can provide users with customized menus. Accordingly, the user can conveniently make selections and submit a request for processing.

Abstract: A shielding apparatus for containing electromagnetic energy is disclosed. In one embodiment, a shield includes a plurality of sides, each side having a top and a bottom. A flange may extend from the top of the sides. A plurality of tabs extend from the flanges. The tabs include a first, second, and third portions. The first portion extends directly from the flange. The second portion extends at an angle from the first portion relative to the plane of the first portion and the flange. The longitudinal axis of the second portion is parallel to its associated flange or side. A third portion extends from the second portion, at an angle relative, to the second portion. A heat sink coated with an electrically conductive material may be mounted such that a bottom side of the heat sink is in contact with the plurality of tabs.

Abstract: A method for a plus one operation includes dividing a binary number into bit sets including a least significant bit set, incrementing the least significant bit set, and, for each bit set other than the least significant bit set, incrementing the bit set unless any less significant bit sets comprises a zero. The bit sets are increment in one of two ways. If all bits of the bit set equal one, e.g., the bit set is 1111, then all bits of the bit set are simply complemented, sometimes called inverted, and set to zero. In all other instances, the least significant zero of the bit set is identified, and the least significant zero and all less significant bits, i.e., everything to the right of the least significant zero, is (are) complemented.