Abstract: A memory system is provided. The memory system is comprised of a memory, a clock signal generator, a phase locked loop circuit, and a bypass circuit. The clock signal generator produces a first clock signal. The clock signal generator has a first mode of operation in which the first clock signal has a first frequency and a second mode of operation in which the first clock signal has a second frequency. The phase locked loop circuit is associated with the memory and adapted for receiving the first clock signal and providing a synchronized second clock signal to the memory. The bypass circuit is adapted to deliver the first clock signal to the memory in the second mode of operation.

Abstract: By including environment information in a security policy, a security architecture advantageously allows temporal, locational, connection type and/or client capabilities-related information to affect the sufficiency of a given credential type (and associated authentication scheme) for access to a particular information resource. In some configurations, time of access, originating location (physical or network) and/or connection type form a risk profile that can be factored into credential type sufficiency. In some configurations, changing environmental parameters may cause a previously sufficient credential to become insufficient. Alternatively, an authenticated credential previously insufficient for access at a given trust level may be sufficient based on a changed or more fully parameterized session environment. In some configurations, the use of session tracking facilites (e.g., the information content of session tokens) can be tailored to environmental parameters (e.g., connection type or location).

Abstract: A method for interpreter optimization includes receiving multiple data units organized according to a first endian order, reordering the data units according to a second endian order and interpreting the reordered data units. According to one aspect, the data units include at least one opcode having at least one operand, each operand including at least one data unit. According to another aspect, a class loader reorders the code within a classfile from big-endian format to little-endian format.

Abstract: A bi-directional output buffer includes active termination and separate driving and receiving impedances. The buffer has at least a driving mode and a receiving mode. In driving mode, the output impedance of the buffer is calibrated to a specified strength. In receiving mode, the buffer is calibrated to another specified impedance as an active termination. In addition, the buffer may be configured such that resistive components are shared in driving and receiving modes.

Abstract: A computer system may include a system memory, an active device configured to access data stored in the system memory, where the active device includes a cache configured to store data accessed by the active device, an address network for conveying address packets between the active device and the system memory, and a data network for conveying data packets between the active device and the system memory. An access right corresponding to a given block allocated in the cache transitions in response to a corresponding data packet being received by the cache. An ownership responsibility for the given block transitions in response to a corresponding address packet being received by the cache. The access right transitions at a different time than the ownership responsibility transitions. The cache is configured to inhibit receipt of the corresponding data packet based on a value of a timestamp associated with the corresponding data packet.

Abstract: A layout and a method for generating a mask for a capacitor are provided. The layout and the mask allow for the formation of the capacitor or an array of capacitors without phase conflict when using phase shift masks in an optical lithography fabrication process.

Abstract: A storage area network (SAN) system that includes a self-contained storage system is managed by a three-tier management system. Management of the self-contained storage system and data services for that system is provided by a three-tiered dedicated management system mirroring the management system that manages the SAN system. In both the SAN management system and the dedicated management system the lowest, or agent, tier comprises Common Information Model (CIM) provider objects that can configure and control the internal components, including the internal switch fabric and disks of both systems. The middle, or logic, tier of the dedicated management system is a set of management facades and federated Java beans. In order to integrate the dedicated management system with the SAN management system, the beans comprising the middle tier of the dedicated management system are also deployed in a shared Jiro™ station associated with the SAN management system.

Abstract: Provided are a computer implemented method, system, and program for discovering components within a network. A discovery operation is initiated to discover a network component. Upon discovering information on one network component, an entry is added to a data store providing information on the discovered component. In response to adding the entry to the data store, at least one of a plurality of programs is called to process the added entry, wherein each called program either accepts or declines to process the added entry. One program accepting to process the added entry initiates a further discovery operation in response to accepting the added entry. A new entry is added to the data store providing information on one network component discovered during the further discovery operation, wherein at least one program is called to process the new entry in response to adding the new entry.

Abstract: A topology based approach to shielding wire generation for an integrated circuit design. The present invention generates various templates by sizing one or more signal wire geometries. The various templates are then geometrically added to and/or subtracted from to generate shielding wire patterns. In some embodiments, the templates may be merged to prevent duplicate shielding wire generation between adjacent signal wires that violates design rules. In some embodiments, the topology based approach permits shielding wire generation based upon complex signal wire geometries, such as branched signal wire geometries. The present invention can be implemented in CAD software and in CAD software together with a small amount of custom software to generate design rule clean (DRC) shielding wire generation that utilizes both power and ground nets.

Abstract: Provided are a method, system, and program for generating information on components within a network. Information is generated on discovered components in the network and a list is generated indicating discovered components in the network. For discovered components indicated in the list, the information on the discovered component is processed to generate a component object representing the discovered component, wherein the component object includes information from the generated information and the information on the discovered component is processed to indicate in the generated component object a relationship to a component object representing a discovered component related to the component represented by the generated object.

Abstract: Provided are a method, system, and program for providing information on components within a network. A user selected host and storage in the network is received and switches are determined to which the selected host and storage connect. Images representing the selected host and storage and all determined switches and connections therebetween are then rendered.

Abstract: Provided are a method, system, program and memory device for providing information on components within a network. Provided is a grouping indicating interconnected components and component objects representing the interconnected components, wherein at least one component object represents a composite component including at least one contained component, wherein each contained component is represented by one component object, wherein relationship information indicates a relationship between each component object representing one composite component and the component objects representing contained components included in the composite component. Further provided are connection objects indicating connections between components represented by component objects. The component objects, the relationship information, and the connection objects are processed to generate output information indicating an arrangement of at least one component within the network.

Abstract: Automated techniques to correct certain rule violations with respect to non-design geometries are used, simplifying and automating the design layout of an electronic circuit, whether embodied as a design encoding or as a fabricated electronic circuit. Correcting minimum spacing rule violations is accomplished by enlarging a design geometry at erroneous boundaries toward one or more non-virtual boundaries of a wide class object of a non-design geometry avoiding one or more shielding areas around one or more virtual edges of the wide class object of the non-design geometry creating an enlarged design geometry; and deducting the enlarged design geometry from the non-design geometry.

Abstract: A method for placing repeater banks in an integrated circuit (IC) design, the IC design including a plurality of circuit blocks placed in an IC design area, the method includes (a) obtaining information of virtual coordinates of virtual repeaters, the virtual repeaters being inserted individually in signal paths between the circuit blocks, the virtual coordinates representing physical location of each of the virtual repeaters in the IC design area, (b) dividing the IC design area into a plurality of sections, (c) determining, for each of the sections, a quantity of the virtual repeaters having the virtual coordinates within the section, (d) clustering, for each of the sections, the virtual repeaters into a repeater bank having a selected size in accordance with the quantity of the virtual repeaters in the section, and (e) assigning to each of the repeater banks a location to be placed within the corresponding section.

Abstract: A method for analyzing test coverage of a software application is provided. The method includes profiling an executable of the software application to generate application call trees. The method also includes profiling test cases used to test a production Java VM so as to generate test case call trees. Also included is comparing the application call trees with the test case call trees so as to identify gaps in the application call tree not covered by the test case call trees.

Abstract: Information concerning CIM classes and instances used to model a managed system is stored in two hash tables that are built at runtime when instances are added to the system. The first hash table, called a subclass table, identifies the subclasses of each CIM class. The second hash table, called an instance table, identifies the instances in the system for each class. The instance and subclass tables are used to retrieve information concerning the CIM instances. In particular, the instance table is used to retrieve all instances of a particular class and the subclass table is used to determine which classes to examine for instances. In one embodiment, the instance table is a hash table that contains a plurality of hash tables. The first hash table, called the primary instance table, contains key-value pair entries, in each entry the key is a CIM class and the value is a secondary hash table that contains the instances of that CIM class. The secondary hash table also contains key-value pair entries.

Abstract: An integrated circuit has a plurality of sections, each having a phase detector and a control delay circuit. The phase detector, in response to a phase difference between a reference clock signal and a feedback signal from a portion of a clock grid, controls the delay of its associated clock delay circuit, which, in turn, outputs to the portion of the clock grid. The feedback signal to the phase detector may be connected to an output of a DLL or another portion of the clock grid controlled by a clock delay circuit not associated with the phase detector. Such an arrangement on the integrated circuit leads to clock grid skew reduction.

Abstract: A method and apparatus are provided that configure a new network device via the network. The method consists of initiating a boot sequence on a first device. The boot process is suspended prior to performing network set up. The new device sends a configuration request to a computer on the network. The computer generates configuration data for the new device and sends configuration data the new device via a multicast message. The new device then writes the configuration data into a file used by an operating system for network configuration on the first device and continues the boot sequence.

Abstract: A method that preferentially shields a signal to increase decoupling capacitance is provided. The signal is preferentially shielded based on a probability of the signal being at a specific value. Because the shield may also be used to form the power and ground grid, a balanced number of power versus ground lines is desired. A method for inverting the signal to balance the number of power versus ground lines is provided. Further, a method to increase system performance by increasing implicit decoupling capacitance is provided.

Abstract: A method for arithmetic expression optimization includes receiving a first instruction defined for a first processor having a first base, the first instruction including an operator and at least one operand, converting the first instruction to a second instruction optimized for a second processor having a second base when all operands do not carry potential overflow or when the operator is insensitive to overflow, the second base being smaller than the first base, and converting to a wider base a third instruction that is the source of the overflow when the at least one operand the potential for overflow and when the operator is sensitive to overflow.