Abstract: A system and method providing address broadcast synchronization using multiple switches. The system for concurrently providing addresses to a plurality of devices includes a first switch and a second switch. The first switch is coupled to receive address requests from a first plurality of sources. The first switch is configured to output the address request from the first plurality of sources. The second switch is coupled to receive address requests from a second plurality of sources. The second switch is configured to receive the address request from the first plurality of sources from the first switch. The second switch is further configured to delay the address request from the second plurality of sources prior to arbitrating between ones of the address request from the second plurality of sources and ones of the address request from the first party of sources received from the first switch.

Abstract: An electronics assembly, for example a computer, comprises an enclosure, and a heat-generating component located within the enclosure. A duct extends from the region of an aperture in a wall of the enclosure to the component and a fan is located within the duct to cause a flow of air from outside the enclosure directly to the heat-generating component.

Abstract: One or more embodiments provide the ability to use multiple path formats in an object oriented system. A path maintains the ability to translate itself into a recognizable format for use by applications. The recognizable format may be a standard Bezier Path format or an iterator that provides the ability to iterate along the path, one curve segment at a time. Multiple applications may use the self-translation ability. In one embodiment, when an application desires to perform a transform, it determines if the transform may be performed on the path (i.e., whether the path is recognizable). If the path is recognizable, the transform is performed directly on the path. If the path is not recognizable, the path translates itself into a recognizable format and the transform performs the action on the recognizable path (the transform must maintain the ability to perform the transform on the standard format). Determining whether the path is recognizable may consist of a two stage negotiation process.

Abstract: One embodiment of the present invention provides a system that facilitates representing a shape within a layout of an integrated circuit using a Boolean expression. The system operates by first receiving a representation of the shape and then converting the representation of the shape into a Boolean expression that is formed using a Boolean coordinate system expressed in a two-dimensional Gray code. The system then performs operations on the shape by performing Boolean operations on the Boolean expression for the shape.

Abstract: A session-aware system and method for caching and serving data. A session-aware cache system stores data that may be designated or restricted for service to registered sessions or data requests that include session identifiers. A request for a restricted set of cached data that omits a session identifier is passed to an origin server (e.g., web server, data server) so that a session may be established and a session identifier assigned. The session-aware cache system may determine whether a session identifier of a data request is near expiration. If so, the request may be passed to the origin server so that the session lifetime may be extended.

Abstract: A method and apparatus for scheduling instructions to provide adequate prefetch latency is disclosed during compilation of a program code in to a program. The prefetch scheduler component of the present invention selects a memory operation within the program code as a “martyr load” and removes the prefetch associated with the martyr load, if any. The prefetch scheduler takes advantage of the latency associated with the martyr load to schedule prefetches for memory operations which follow the martyr load. The prefetches are scheduled “behind” (i.e., prior to) the martyr load to allow the prefetches to complete before the associated memory operations are carried out. The prefetch schedule component continues this process throughout the program code to optimize prefetch scheduling and overall program operation.

Abstract: The invention is directed to a method and apparatus for simulating a digital logic circuit simulator. In particular, a block object, representing a component of the digital logic circuit, is instantiated. An event object having a queue is also instantiated. The queue holds an ordered list of destinations, which are representative of the block objects that the event object initiates an action with. When the event object interacts with the block object, this initiates behavior in the block object indicative of behavior of the component in the digital system. The digital logic circuit simulator components, namely the block object and the event object, can be instantiated in a run-time object oriented language, such as the JAVA® language promulgated by Sun Microsystems. The block object can initiate a dynamic addition to the destination queue. Additionally the destination can be another event object. When the destination is another event object, another event object is initiated.

Abstract: A method creates a proxy auto-configuration file for a system including a plurality of proxy servers. The method includes accessing and performing a performance test on each of the plurality of proxy servers, and creating a proxy auto-configuration (PAC) file in response to the performing. The PAC file may be posted on a web server. The method may further include iteratively updating the PAC file by periodically conducting the accessing, the performing, and the creating. The creating the PAC file may include generating a list of a selected number of best-performing proxy servers among the plurality of proxy servers. The performing the performance test may include sending a command to fetch at least one selected web page, receiving the selected web page, and determining an amount of time required to fetch the selected web page.

Abstract: Counting events during the execution of one or more instructions in a computer system may be accomplished by maintaining a non-speculative counter for counting events occurring in non-speculative instructions, as well as a separate speculative counter for counting events occurring in speculative instructions. Event counters may be used to count individual events occurring during the processing of instructions. When the instruction has been completed, the amount in the event counter corresponding to a particular event for that instruction is added to the amount in the speculative counter corresponding to the event. Then, any retirable instructions are retired. Once an instruction is retired, it is no longer speculative, allowing the amount in the speculative counter to be decremented and the amount in the non-speculative counter to be incremented by the amount in any event counters corresponding to retirable instructions.

Abstract: An efficient method is described for laying out a table for display. The method may be used to display tables on a small footprint device, such as a smart cellular phone, a personal data assistant, a handheld computer, etc. Small footprint devices typically have smaller displays than other computing systems such as desktop computers. In one embodiment the method is employed to lay out HTML tables in a web browser running on a small footprint device.

Abstract: A method and apparatus of supporting an audio protocol in a network environment. Audio processing and hardware requirements associated with a receiver are minimized by specifying a single audio protocol for transmission of audio data between transmitters on a network and the receiver. The protocol specifies a sampling rate, bit resolution and quantization scheme which allow for high sound quality and further minimize the complexity of the receiver. Transmitters are equipped with drivers to provide for conversion of audio data into the designated protocol as needed. Aspects of the designated protocol are provided to compensate for problems associated with transmitting audio streams over a network. The designated protocol specifies a format for interleaving audio samples within data packets to minimize errors which are the result of consecutive missing audio data samples due to packet loss. The receiver may further compensate for missing audio data samples through interpolation.

Abstract: A storage system is described including a two dimensional array of disk drives having multiple logical rows of drives and multiple logical columns of drives, and at least one drive array controller configured to store data in stripes (e.g., across the logical rows). A given drive array controller calculates and stores: row error correction data for each stripe of data across each one of the logical rows on one of the drives for each row, and column error correction data for column data grouped (i.e., striped) across each one of the logical columns on one of the drives for each column. The drive array controller may respond to a write transaction involving a particular row data stripe by calculating and storing row error correction data for the row data stripe before completing the write transaction.

Abstract: Internally generating test vectors on a microchip during a burnin stage allows for better toggle coverage while not requiring external memory. A test access port (TAP) controller which accepts signals from a user and indicates to a linear feedback shift register (LFSR) that the microchip is in the burnin stage. The LFSR then may generate a set of pseudorandom values using a polynomial. The values are then shifted one per clock cycle into the internal scan chain of flips-flops on the chip, which toggles the internal state of the chip. New pseudorandom values are also generated one-by-one during the shift. By using this approach, the internal states of the chip are toggled without the use of an external memory for the burnin system.

Abstract: A method, apparatus, and computer program product for handling IEEE 754 standard exceptions for Single Instruction Multiple Data (SIMD) instructions. Each SIMD sub-operation's corresponding IEEE 754 exception flag is bit-wise “ORed” with an accrued exception field if a trap enable mask field is configured to mask the exception, with the “ORed” result written back in the accrued exception field. If the trap enable mask field is configured to enable the exception, the accrued exception field and a current exception field are cleared, and an unfinished floating-point exception flag is set in a floating-point trap type field. The actual sub-operation(s) causing the exception is determined through software.

Abstract: A method and apparatus for packaging and distributing software. Embodiments of the invention comprise a software packaging system that is portable across many platforms. Each package is self-contained in form of a single-file entity that comprises a payload file and a control file. The payload file is an archive file that contains a compressed collection of all the software files that are required for installation of the software package. The control file includes the necessary information for installation of the files contained in the payload file, in addition to other descriptive information used to determine the size, type, location of storage, and other useful attributes of a software package, even before it is installed on a system. Security measures have been implemented in the system to detect a package the contents of which have been tampered with. Embodiments of the invention can be utilized to install packaged software that is accessible via the Internet.

Abstract: In general, the invention relates to a method for optimized execution of a computer program including detecting a preservable static field in said computer program with a compiler, comprising detecting at least one selected from the group consisting of a getstatic instruction and a putstatic instruction, annotating said preservable static field to create an annotation indicating whether said field is preservable, compiling said computer program to produce an output using said annotation, wherein said output includes information about said field, encoding said output if backward compatibility is required, loading said output, and executing said output in an environment.

Abstract: A CPU is provided with an ability to modify its operation in accordance with an encryption key. When a program is compiled, the program is modified in order that execution may be performed by the CPU with modified op codes. As a result, it is unnecessary to decrypt the program into standard op codes prior to execution. The modified op codes are provided with surplus bits, causing an increase in op code length, and the output of data results is provided in blocks of several words. The internal allocations of signals and logic gates is made key dependent to further foil the efforts of adversaries who may attempt to understand the program instructions.

Abstract: The Sharing arbiter is an arbiter which, under certain conditions, permits two or more Done signals to be received before the Sharing arbiter issues a grant signal and, under certain conditions, is permitted to issue more than one grant signal before receiving a Done signal. A Sharing arbiter can be implemented by adding a queue onto the Done input of a Sequencer arbiter. In a Sharing arbiter with a Sharing-number of N and K request inputs, the Sharing arbiter is permitted to issue M grant signals concurrently if M input requests have been received (where M≦K and M≦N) without enforcing mutual exclusion between the grants if at least M Done signals have also been received. Where less than M Done signals have been received (P Done signals, for example), the Sharing arbiter arbitrates among the M input requests and is permitted to issue P grant signals concurrently.

Abstract: Apparatus and methods for achieving a desired value of electrical impedance between parallel planar conductors of an electrical power distribution structure by electrically coupling multiple bypass capacitors and corresponding electrical resistance elements in series between the planar conductors. The methods include bypass capacitor selection criteria and electrical resistance determination criteria based upon simulation results. An exemplary electrical power distribution structure produced by one of the methods includes a pair of parallel planar conductors separated by a dielectric layer, n discrete electrical capacitors, and n electrical resistance elements, where n≧2. Each of the n discrete electrical resistance elements is coupled in series with a corresponding one of the n discrete electrical capacitors between the planar conductors. The n capacitors have substantially the same capacitance C, mounted resistance Rm, mounted inductance Lm, and mounted resonant frequency fm-res.

Abstract: A module and a corresponding connector that include multiple rows of contacts is described. In one embodiment, the module may include a channel formed in a bottom edge of the module. A plurality of contacts may be disposed on the inner surface of the channel and the outer surface of the module. A complementary connector is also described.