Abstract: Provided is a method, system, program, and data structure for applying a patch to a computer system, wherein the patch includes content to add to the computer. A computer object is generated to include configuration information on the determined installed components. At least one patch includes content to add the computer and is capable of being associated with at least one realization, wherein each realization defines a state of the computer. For each realization, a determination is made from the configuration information in the computer object as to whether the state defined by the realization exists in the computer. Data is written to the computer object indicating whether the state defined by the realization exists on the computer. The computer object is used to determine whether each patch is compatible with the installed components of the computer.

Abstract: A method, apparatus and system arranged to provide a contract between an application server and a resource adapter that allows the resource adapter to do work (monitor network endpoints, call application components, etc) by submitting work instances to an application server for execution. In the described embodiment, the application server dispatches threads to execute submitted work instances thereby allowing the requesting resource adapter to avoid creating or managing threads directly. In this way, a mechanism for the resource adapter to do its work is provided as well as allowing the application server to efficiently pool threads and have more control over its runtime environment.

Abstract: Provided is a method, system, program, and data structure for determining patches to apply to a computer system, wherein the patch includes content to add to the computer. A realization list of realization identifiers corresponds to realizations associated with the computer, wherein each realization defines a state of the computer. A realization database includes realization objects, wherein each realization object is uniquely identified by a realization identifier of one realization and includes a patch list indicating those patches whose installation relates to the computer state defined by the realization. The patch lists are accessed from the realization database for those realization objects whose realization identifiers match the realizations identifiers on the realization list. A determination is made of all the patches on the accessed patch lists. A determination is made from the determined patches on the accessed patch lists those patches that are capable of being installed on the computer.

Abstract: An integrated circuit includes an address register, clocked by the clock signal corresponding to the TAP, used to address a control/status register within the integrated circuit. The address register receives a signal indicating that an address is to be loaded into the address register. A control circuit is coupled to receive the signal and to generate a second signal responsive to the address register being loaded. A shadow register, clocked by the clock signal of the integrated circuit, is coupled to receive the second signal and to load a value from the control/status register addressed by the address loaded into the address register responsive to the second signal. In this manner, a valid value from the addressed register is synchronized in the clock domain of the addressed register. The value for the shadow register may subsequently be synchronized into the clock domain of the TAP, and subsequently transferred out of the integrated circuit via the test interface.

Abstract: An electronics assembly comprises a frame (1) that contains a motherboard (8) and a plurality of daughterboards (10). The frame has an opening opposite the motherboard to allow insertion of the daughterboards into the frame or removal of the daughterboards from the frame. The frame also has an injector/ejector mechanism (16, 18) for each daughterboard that is located on the daughterboard or the frame and a flange (28) that extends adjacent to the opening and on which the injector/ejector mechanism of each daughterboard is attached or engages at different locations along the length thereof. The flange (28) is divided into separate sections (30) that correspond to the different locations to allow the flange to flex at any adjacent location during insertion of a daughterboard without the flexing affecting the position of any adjacent location of the flange with respect to the motherboard.

Abstract: One embodiment of the present invention provides a system that detects cycles in a set of dependencies between a set of resources in a computer system. The system operates by receiving a new dependency indicating that a first resource cannot proceed unless a second resource is able to proceed. The system determines if the new dependency creates a cycle in the set of dependencies by performing a search, which looks for cycles of dependencies starting from the first resource and ending at the first resource. If the search detects such a cycle, the system indicates that the new dependency creates the cycle. The system may also send an error message when the cycle is detected, and may abort further processing. In one embodiment of the present invention, the new dependency between the first resource and the second resource indicates that the second resource must be started before the first resource is started.

Abstract: One embodiment of the present mechanism provides a system for storing long-lived objects defined within an object-oriented programming system. These long-lived objects are created in a virtual machine used for executing platform-independent code and are ordinarily created during initialization of the virtual machine. The system works by allocating a storage area reserved for long-lived objects that is not subject to garbage collection. After the storage area is allocated, the system receives requests to create an object. The system then determines if the object is a long-lived object by referring to a table of long-lived objects. If the object is a long-lived object, it is created and placed in the reserved storage area.

Abstract: A system and method for detecting parity errors in a system where clients are configured to arbitrate amongst themselves for a grant to a central resource is provided. A client may send a request for access to the central resource to all other clients. In the event that multiple clients request access to the central resource substantially simultaneously, the clients may each determine which client should be granted the right to send its request to the central resource. The clients may make this determination according to an arbitration scheme. Where multiple requests occur substantially simultaneously, each client may calculate a parity based on the number of requests it receives. The clients may each convey their parity to the central resource. The clients may convey these parities to the central resource at about the same time as the granted request is conveyed to the central resource by its respective client.

Abstract: Methods and apparatus for enabling an efficient generational scavenging garbage collection to be performed on a managed memory area are disclosed. According to one aspect of the present invention, a method for reclaiming memory space uses a managed memory area that includes a first area and a second area. The first area is arranged to store recently allocated objects, while the second area being arranged to store older objects. The method includes determining when a first section of the first area in which new objects are to be allocated is substantially filled. When it is determined that the first section is substantially filled, a garbage collection is performed on a second section of the first. After the garbage collection, the second section is set to support new object allocation such that new objects are allocated in the second section, while the first section is reset such that it is no longer arranged to support new object allocation.

Abstract: The present invention is a module insertion tool for anchoring a module to a motherboard. The module insertion tool has two drivers on either side of the tool that operate independently of each other, and help in anchoring the module to the motherboard. There is a knob built into the tool. The knob is connected to a chain that turns the drivers until a preset torque value is reached. The two drivers built into the tool are independent of each other and each driver turns until the preset torque value has been reached. This preset torque value can be obtained by either manually turning the knob, or by attaching an electric source to a socket built into the knob. There are three locators on a bottom plate of the tool that help in the alignment of the module to the tool, and there are locking pins on each driver that hold the module stationary while the module is being anchored to the motherboard by the drivers of the tool.

Abstract: A method and tool for simulating a multiple input signature register for a memory test application is provided. Further, a method and tool for signature simulation based on a configuration, type, and/or size of a memory structure is provided. Further, a method and tool for multiple input signature register simulation for a memory built-in self test application is provided.

Abstract: One embodiment of the present invention provides a system that prefetches instructions by using an assist processor to perform prefetch operations in advance of a primary processor. The system operates by executing executable code on the primary processor, and simultaneously executing a reduced version of the executable code on the assist processor. This reduced version of the executable code executes more quickly than the executable code, and performs prefetch operations for the primary processor in advance of when the primary processor requires the instructions. The system also stores the prefetched instructions into a cache that is accessible by the primary processor so that the primary processor is able to access the prefetched instructions without having to retrieve the prefetched instructions from a main memory. In one embodiment of the present invention, prior to executing the executable code, the system compiles source code into executable code for the primary processor.

Abstract: Repeating image content in a graphics image may be detected by identifying certain commands, known generally as “tile commands”. If a tile command is detected, the fact that a portion of an image was created with a tile command may be stored along with the portion of the image. This allows for well-informed decision making when transmission of the image is to be performed. For example, this allows for the transmission of a single tile, and subsequent transmission of local copy commands to repeat the single tile. This can be very useful in speeding transmission of background images or other repeating images.

Abstract: A solution is provided to reshape irregularly-shaped computer graphics images in order to reduce the number of rectangles generated for transmission. It may be used any time it is useful to compress a set of digital image data from an irregularly-shaped region of pixels. A post-shaping process may be utilized wherein rectangles in a destination window are examined and any touching (or possibly nearby) rectangles are merged into a single rectangle. Alternatively, a pre-shaping process may be utilized wherein images drawn with a single command are merged into a single rectangle. Each of these processes has advantages and disadvantages which may make one or the other preferable, depending upon the circumstances. Additionally, both processes may be used together if desired.

Abstract: The storing of not only image content but information regarding what commands were used to create the image allows for well-informed decision making. The drawing commands are recorded and may be stored in a data structure. This data structure may then be accessed at the time of compression, and the selection of which compression technique to use may be based on the drawing commands. Pixmaps are data structures holding pixel values corresponding to an image in memory. The data structure utilized here may be a linked list identifying fill regions. This permits the well-informed decision making to be accomplished even when pixmaps are copied to realized (on-screen) windows or other pixmaps.

Abstract: The storing of not only image content but information regarding what commands were used to create the image allows for well-informed decision making. The drawing commands are recorded and may be stored in a data structure. This data structure may then be accessed at the time of compression, and the selection of which compression technique to use may be based on the drawing commands. Thus, certain codecs may be applied to certain portions of the image, resulting in a more efficiently compressed image. Pixmaps are data structures holding pixel values corresponding to an image in memory. The data structure utilized here may be a separate RGB pixmap region associated with a pixmap holding image data. This permits the well-informed decision making to be accomplished even when pixmaps are copied to realized (onscreen) windows or other pixmaps.

Abstract: A system for distributing power in a compact peripheral component interconnect (CPCI) computer architecture is provided. A CPCI computer architecture comprises a plurality of CPCI systems each having respective backplanes. The backplanes further having respective local power rails providing power for a corresponding one of the plurality of CPCI systems. The power distribution system provides power to the backplanes, and comprises a common power rail connected to each one of the local power rails of the backplanes. A plurality of power supplies is connected to the common power rail of the power distribution system. Power taken from any one of the plurality of power supplies is available to any one of the backplanes.

Abstract: The present invention provides an automated problem identification system. The invention analyzes a customer's computing environment, including administration practices, system configuration including hardware, software and the operating system. Then the invention compares the computing environment to an internal rules database. The internal rules database is a compilation of various problems that are known to exist on various configurations. Then, instead of calling an expert when there is a problem and repeating the process for every customer, the invention uses a proactive approach by analyzing a given system configuration and comparing it to a body of known problems, before the system breaks down.

Abstract: The invention is a method and apparatus for synchronizing firmware associated with a first computer device and a second computer device, such as a server and a client computer. In accordance with one embodiment of the invention, the method comprises the steps of providing information regarding a characteristic of the firmware associated with the first and second devices, comparing the provided firmware information to determine if the firmware is synchronized, and associating new firmware with the second device to synchronize the firmware if the firmware is found to not be synchronized in the comparing step. In one or more embodiments of the invention, the firmware associated with the second device is not modified unless the integrity of the firmware to be installed on the second device is verified using a digital signature.

Abstract: A computation unit employs a logarithmic number system that uses a logarithmic numerical representation that differs from an IEEE standard representation to improve the efficiency of computation, both by reducing the time expended in performing the computation and by reducing the size of the integrated circuit that performs the computation. The illustrative computation unit employs a numerical representation that is similar to the IEEE format except that the sign term is omitted. Thus only positive numbers are represented. The value of the mantissa is defined as a fractional number between zero and one. The logarithmic number system is a useful number system domain for multiplication, division, reciprocal, square root, and power computations using multiplication, division, and square root computation techniques described by following equations: A*B=Anti-log(log(A)+log(B)),  (3) A/B=Anti-log(log(A)−log(B)),  (4) B½=Anti-log(log(B)/2).